REVERSIBLE LOGIC SYNTHESIS

Overview of the Presentation 1. Introduction 2. Design of a Reversible Full-adder Circuit

Part 1 Introduction

The gate/circuit that does not loose information is called reversible. What is Reversible Logic / Reversibility ? Input Vector I v =( I i,j, I i+1,j, I i+2,j, …, I k-1,j, I k,j ) Output Vector O v =( O i,j, O i+1,j, O i+2,j, …, O k-1,j, O k,j ) For each particular vector j I v  O v Def n 1: A Reversible circuit has the facility to generate a unique output vector from each input vector, and vice versa.

What is Reversible Logic / Reversibility ? (cont.) Def n 2: Reversible are circuits in which the number of inputs is equal to the number of outputs and there is one-to-one mapping between vectors of inputs and outputs. Reversible Gate i i i i i K-1 K O O O O O K A gate with k inputs and k outputs is called k*k gate.

Difference Between Reversible Gate and Irreversible Gate Truth Table For Irreversible EXOR Logic InputsOutput ABC = A B

Difference Between Reversible Gate and Irreversible Gate (cont.) Truth Table For Reversible EXOR Logic (Feynman Gate) InputsOutput ABP=AQ = A B

It has been proved ( by Bennett and Landauer [1]) that, “losing information in a circuit causes losing power. Information lost when the input vector cannot be uniquely recovered from the output vector of a combinational circuit”. The gate/ circuit does not loose information is called reversible. Motivation Towards Reversible Gate

Garbage Bit Every gate output that is not used as input to other gate or as a primary output is called garbage. The unutilized outputs from a gate are called “garbage”. Heavy price is paid off for every garbage output. A B P = A * Q = A B

Some Popular Reversible Gates P = A ' A Not Gate AP x 1 Not Gate

Some Popular Reversible Gates (cont.) A B P = A Q = A B Feynman Gate AB PQ x 2 Feynman Gate (CNOT Gate) [2]

Some Popular Reversible Gates (cont.) A B Toffoli Gate C P = A Q = B R = AB C ABC PQR x 3 Toffoli Gate [3]

Some Popular Reversible Gates(cont.) A B Fredkin Gate C P = A Q = A ' B AC R = A ' C AB ABC PQR x 3 Fredkin Gate [4]

Some Popular Reversible Gates(cont.) A B New Gate C P = A Q = AB C R = A'C' B' ABC PQR x 3 New Gate (Khan Gate) [5]

Some Popular Reversible Gates(cont.) A B Peres Gate C P = A Q = A B R = AB C ABC PQR x 3 Peres Gate[6]

Different Modes of Feynman Gate 0 B P = 0 Q = B Feynman Gate All possible cases in 2 x 2 Feynman Gate A as control input Output B as control input Output PQPQ 00B 0AA 11 B'B' 1AA' 1 B P = 1 Q = B ' Feynman Gate A 0 P = A Q = A Feynman Gate A 1 P = A Q = A ' Feynman Gate

Realizations of Irreversible Gates Using Reversible Gates A B Toffoli Gate 0 P = A Q = B R = AB 0 = AB InputOutput ABC A B AND GATE C = AB AND GATE

Realizations of Irreversible Gates Using Reversible Gates(cont.) A B Toffoli Gate 1 P = A Q = B R = AB 1 = AB InputOutput ABC A B NAND GATE C = AB NAND GATE

Realizations of Irreversible Gates Using Reversible Gates(cont.) A B Toffoli Gate 1 P = A Q = B R = A B 1 =A B =A + B InputOutput ABC A B OR GATE C = A + B OR GATE

Realizations of Irreversible Gates Using Reversible Gates(cont.) A B Toffoli Gate 0 P = A Q = B R = A B 0 = A + B InputOutput ABC A B NOR GATE C = A + B NOR GATE

Reversible Network Structure

The main rules for efficient reversible logic synthesis Use as many outputs of every gate as possible, and thus minimize the garbage outputs. Do not create more constant inputs to gates that are absolutely necessary. Avoid leading output signals of gates to more than one input( Fanout). Don’t use any feedback loop; it is strictly restricted. Use as less number of reversible gates as possible to achieve the goal. The main rules for efficient reversible logic synthesis

Part 2 Design of a Reversible Full-adder Circuit

Input Output ABC in SumC out Design of a Reversible Full-adder Circuit Sum=A B C Carry=AB + BC + CA =AB BC CA

Design of a Reversible Full-adder Circuit(cont.) Sum=A B C Carry=AB + BC + CA =AB BC CA A B EXOR GATE A B EXOR GATE Sum AND GATE AND GATE AND GATE C EXOR GATE EXOR GATE Carry

Design of a Reversible Full-adder Circuit Sum=A B CCarry=AB + BC + CA =AB BC CA A B P = A Q = A B Feynman Gate Q = A B C = Sum Feynman Gate P = A B C

Design of a Reversible Full-adder Circuit (cont.) Sum=A B C Carry =AB BC CA A B Toffoli Gate 0 P = A Q = B R = AB B C Toffoli Gate 0 P = B Q = C R = BC C A Toffoli Gate 0 P = C Q = A R = CA P = AB Q = AB BC Feynman Gate P = AB BC Q = AB BC CA= Carry Feynman Gate

Design of a Reversible Full-adder Circuit (cont.) Sum=A B CCarry= =AB BC CA = (A C)B CA A B Toffoli Gate 0 A B AB C Toffoli Gate A B C (A C)B CA = Carry A A B Feynman Gate P = A B Q = A B C = Sum Feynman Gate

Three Gates & Three Garbage outputs [5] Four Gates & Two Garbage outputs [7] Existing Reversible Full-adder Circuits

Two Gates & Two Garbage outputs Three Gates & Two Garbage outputs Proposed Reversible Full-adder Circuits

Comparative Results Gates Garbage Outputs Existing 1 42 Existing 2 33 Proposed 1 32 Proposed 2 22

Input Section Output Section ABC in Sum (S)C out Theorem: A reversible full-adder circuit can be realized with at least two garbage outputs

A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) Input Section Output Section ABC in SC out G

A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) Input Section Output Section ABC in SC out G1G1 G2G

References [1] C. H. Bennett. Logical reversibility of computation, IBM J. Research and Development, 17:pp , November [2] R. Feynman, Quantum Mechanical Computers, Optical News (1985) [3] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980). [4] E. Fredkin, T Toffoli, Conservative Logic, International Journal of Theor. Physics, 21(1982), pp [5] Md. M. H Azad Khan, Design of Full-adder with Reversible Gates, International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp , [6] Peres, A., Reversible Logic and Quantum Computers, Physical Review A, 32: , [7] A. Mishchenko and M. Perkowski. Logic synthesis of reversible wave cascades. International Workshop on Logic Synthesis, pages , June 2002.

The End REVERSIBLE LOGIC SYNTHESIS