© Janice Regan, CMPT 300, May CMPT 300 Introduction to Operating Systems Principles of I/0 hardware

© Janice Regan, CMPT 300, May Controlling I/O  One of the most complex jobs done by the OS is to manage input and output  The job is complex because  There are many different types of I/O devices  Different I/O devices operate at different data rates  There are different approaches to controlling I/O that must be considered when designing the system (hardware and software)

© Janice Regan, CMPT 300, May Types of I/O devices  Human readable devices  Printers  Terminals/workstation monitors  Plotters  Machine readable  Keyboard, Mouse, touch screen  Disk drives  Tape drives  Sensors,  Communication with remote devices  Network card  modem

© Janice Regan, CMPT 300, May Important considerations  Data rate  Data representation:  Encoding  Error checking:  How to detect and deal with errors  Transfer unit  Byte stream (character device)  Block by block (block device)  Complexity of hardware and software needs

© Janice Regan, CMPT 300, May Approaches to I/O  The simplest approach: Programmed I/O  CPU issues an I/O command  CPU busy waits (or polls) while I/O is completed  Interrupt Driven (byte stream)  CPU issues an I/O command to I/O device  CPU enters wait state  CPU continues with other processing (same or more likely different process)  I/O device generates an interrupt when it finishes and the CPU finishes processing the interrupt before continuing with its present calculations.  DMA (also interrupt driven) block transfer

© Janice Regan, CMPT 300, May Evolution of I/O  Direct processor control  I/O control module added: programmed I/O (no interrupts)  I/O control module make CPU independent execution of single byte I/O possible, use interrupts for efficiency  I/O control module given direct control for block transfer (early DMA). CPU only involved at start and end of transfer.  Enhanced I/O module (separate processor). Single user instruction to set up DMA for transfer. Can specify a series of I/O instructions as process, dowload process to I/O module and interrupt CPU only after all of them (the process) are complete.

© Janice Regan, CMPT 300, May Device controllers/drivers  Hardware units that are able to independently control the I/O device (without CPU intervention)  Controllers handle one or more devices of a particular type  Generally different I/O devices have different needs and will have their own particular controller  The controller generally processes a serial bit stream, usually buffering (particularly for block transfer devices and to help match different transfer rates)  The controller usually performing error detection / correction to assure error free transfer of each block (preamble with block identification, a checksum using error correction code)  The device driver is the software that it written to make the controller function. Without device drivers each application would have to explicity control all aspects of I/O from controlling the head on the disk drive to displaying line by line or pixel by pixel on the screen.

© Janice Regan, CMPT 300, May I/O control registers  Each device controller has registers that control operation  DMA has registers for read/write, I/O device address, block size, starting destination address, state  The controller must communicate with the CPU (the user process) to place values or check values in these registers  There may also be a data buffer as part of the controller. This data buffer is usually in the memory space of the OS, not the user process

© Janice Regan, CMPT 300, May CPU-register communication  Simplest approach:  Assembler language commands  Each controller register is assigned a port number  Command specifies controller register by port number, CPU register by name or address (two different address spaces)  Transfer of one value to one controller register is one assembler language instruction  More sophisticate approach  Memory mapped I/O  Hybrid systems use memory mapping for I/0 data buffers and ports for data registers (Pentium)

Memory region For I/O controller Buffers + registers OS Process N Process M Systems with 2 address spaces © Janice Regan, CMPT 300, May OS Memory region for I/O buffers Process N Process M Memory region for I/O registers HYBRI D SYSTE M

© Janice Regan, CMPT 300, May Memory mapped I/O  Map all control registers into the memory space  Memory map will have a block of addresses that physically corresponds the registers on the I/O controllers rather than to locations in main memory OS Memory region for I/O controller registers Process N Process M Memory map

© Janice Regan, CMPT 300, May Advantages: memory mapped I/O  Allows device drivers and low level control software to be written in C rather than assembler  Normal assembler instructions to access memory can be used to directly access controller registers  Every instruction that can access memory can also access controller registers, reducing the number of instructions needed for I/O  Can structure the system so that only needed drivers are loaded into user program (page per driver)  OS can have better control over controller registers

© Janice Regan, CMPT 300, May Disadvantages: memory mapped I/O  Need additional complexity in the OS  Cannot cache controller registers  Changes made in cache do not affect the controller!  Must assure that the memory range reserved for memory mapped controller registers cannot be cached. (disable caching)  All memory and I/O modules must examine all memory references  Optimized architectures with other bus structures may require special support for memory mapping

© Janice Regan, CMPT 300, May Single Bus: memory mapping  CPU sends requested address along bus  Bus carries one request/reply at a time  Each I/O device controller checks if requested address is in thier memory space  Device controller whose address space does contain the address replies with the requested value from that address CPUmemoryI/O

© Janice Regan, CMPT 300, May Memory Bus: memory mapping  Common to have high speed bus for memory access (e.g. pentium)  Memory accesses meant for mapped I/O registers will go to main memory along the high speed memory bus!  Use a dedicated filter (chip) to determine which bus to send to  Send to memory first, then bus if not found CPUmemoryI/O

© Janice Regan, CMPT 300, May Using DMA  DMA is used to transfer data between disk and memory (or disk and disk, memory to memory)  Disk access is much slower than memory access. Must assure that data is available when memory is ready (use buffering)  Transfer data in blocks  each block read from disk will be placed in a buffer from which the DMA can transfer it to memory  each block written to disk will be placed in a buffer by the DMA for later transfer to disk  The buffer is part of the disk controller  Also allows each block’s data to be checked for transfer errors

© Janice Regan, CMPT 300, May 2007 Disk read: without DMA  CPU requests data  Disk controller reads a block of data into its buffer. Data is read serially, bit by bit into the buffer.  The integrity of the transferred data block is verified  Controller sends interrupt to CPU indicating transfer to buffer is done  CPU can transfer from buffer to memory one byte or word at a time 16 CPU buffer Memory Disk controller b 5a 5c

Why a buffer?  Allows the controller to verify block of data is correct (has not been corrupted) by doing a checksum  Reduces problems due to bus contention  Avoids problem of another word arriving from disk before the current word has been transferred across the bus to the memory.  This problem can be common when the bus is busy, or when a burst transfer is occuring © Janice Regan, CMPT 300, May

© Janice Regan, CMPT 300, May DMA operation: using disk  CPU sends information to instruct DMA  DMA requests disk controller put block of data into its buffer and verify the integrity of the transferred data  Until all data is written to memory the following steps are repeated a. DMA sends data transfer request to disk controller. b. The disk controller writes a word from buffer to memory  The disk controller acks to the DMA  DMA sends interrupt to CPU indicating transfer is done CPU DMA addresses port Read/write count buffer Memory Disk controller 1 2 3b 3c 4 3a

More sophisticated DMAs  Can service more than one request at a time  Include multiple sets of registers to control multiple simultaneous transfers  Each transfer must be talking to a different device controller  Data transfer requests are made in some sequence (round robin of active transfers etc)  Sometimes differentiate acks by using different physical line in the bus. This will provide an unambiguous way to tell acks from different controllers apart  Can operate in different modes (parallel available bus modes) © Janice Regan, CMPT 300, May

© Janice Regan, CMPT 300, May DMA: transfer modes  Cycle Stealing  DMA requests Disk controller to send one word at a time  Each time a word is transferred bus must be requested and acquired then data sent and ack received  Requests interleave with CPU bus requests, CPU may have to wait for bus in some cases  Words may go directly or through DMA (more flexible allows memory to memory and disk to disk transfers)  Block Mode  One request made for bus (increases efficiency)  Entire block transferred  Ack sent  Bus becomes available for other users  CPU may have to wait for block transfer to complete before it can reacquires bus

© Janice Regan, CMPT 300, May IO bus CPUmemoryDMAI/O CPUmemory I/O DMA