The Trigger Prototype Board Status Marco Grassi INFN - Pisa On behalf of trigger group D. Nicolò F. Morsani S. Galeotti M. Grassi

Hardware: board Type 1 VME 6U A-to-D Conversion –FADC with differential inputs bandwidth limited Trigger –LXe calorimeter –timing counters No use for the tracking chambers I/O –16 PMT signals –2 LVDS transmitters –4 in control signals FADCFPGA Control FPGA PMT x VME Sync Clock Sync Trigger Start 4 LVDS Trans 48 LVDS Trans Type 2 boards

Hardware: board Type 2 VME 9U Matched with the Type 1 boards I/O –10 LVDS receivers –2 LVDS transmitters –4 in control signals –3 out signals FPGA Control FPGA Type 1 10 x Sync Clock Sync Trigger Start 4 VME LVDS Trans LVDS Trans 48 LVDS Rec x 18 to next Type 2 Trigger Sync Start 3 Out 3

Type2 Hardware: system structure LXe inner face (312 PMT) Type boards 20 x 48 Type Type2 2 boards boards 10 x 48 Type LXe lateral faces (208 PMT) (120x2 PMT) (40x2 PMT) Type2 1 board or 6 boards 12 x 48 Type Timing counters (160 PMT) or (80 PMT) Type2 2 or 1 boards 4 x 48 1 board 4 x 48 2 x 48 2 VME 6U 1 VME 9U

Present status Prototype board: Type0 –Modified Type1 : Check of the connectivity with the Type2 Study the FADC coupling Verify the chosen algorithms Selected components (all delivered) Main FPGA XCV812E-8-FG900 and XCV18V04 config. ROM Interface and control CPLD XC95288XL-FG256 ADC AD9218 (dual 10 bits 100 MHz) Clock distribution CY7B993V (DLL multi-phase clock buffer) LVDS serializer DS90CR483 / 484 (48 bits MHz Gbits/s) LVDS connectors 3M Mini-D-Ribbon Analog input by 3M coaxial connectors Control and debug signals in LVDS standard FPGA design completed –FPGA design and simulation completed (runs at 100 MHz) –VHDL parameterization is ready

Prototype board : Type 0 VME 6U A-to-D Conversion Trigger I/O –16 PMT signals –2 LVDS transmitters –4 in/2 out control signals Complete system test LVDS Rec Sync Trigger Start FADCFPGA Control CPLD PMT x VME Sync Clock Sync Trigger Start 4 48 LVDS Trans 3 Out 2 boards 16 4 Type0 Trigger Start 4 Analog receivers Spare in/out

The Analog input stage BW limitation Unipolar or bipolar inputs Variable gain Pedestal adjust AD8138

Board Design  completed –Implementation by means of CADENCE –Schematic simulation completed –Components footprints checked –Board routing  ready 10 layers 4 GND Power 6 signals DC/DC converters A32 mode Block transfer Board production –PCB producer contacted: ready for a production offer –Delivery: end of July –Test: September

DRS Chip Prototype received Nov. 02 Tests Dec. 02 – April 03 Digital part works perfectly Analog parts requires redesign DLL and VME board built by Siena Prototype received Nov. 02 Tests Dec. 02 – April 03 Digital part works perfectly Analog parts requires redesign DLL and VME board built by Siena

Test results f samp [GHz] vs. V control [V] f samp [GHz] vs. V dd [V] f samp [GHz] vs. T[deg. C]

Running Domino Wave D enable D tap Jitter after 32 turns: ~1ns 32 Domino 320ns SR_CLK SR_RESET SRIN SROUT #768 Readout Shift Register

DLL Design R. Paoletti, N. Turini, INFN In Phase Comparator Ext. quartz clock DLL V speed DLL works with jitter of 200 ps RMS Siena (N. Turini, R. Paoletti, MAGIC) designs VME board

DRS Readout Input pulseDigitized output pulse 5ns risetime 8ns risetime

Problems in analog part PHI Bus C samp source drain gate Capacitances: Gate-Bulk:10.6 fF Source-Bulk: 13.5 fF Drain-Bulk:2.4 fF Bus capacitance too high (110pF)

DRS Redesign Reduce bus-bulk capacitance by 6x Reduce bus-bus capacitance Use current-mode readout write read C... R I V out G. Varner, Univ. of Hawaii: STRAW2 chip V in

Plans UMC 0.25  m technology Next Submission Oct. 20 th Production time ~9 weeks VME board design in parallel (Siena) Rectangle 5 x 5 mm 2 Reduce minimum sampling speed to 500 MHz (for DC) Daisy chain mode for N x 1024 bins Dual-channel for deadtimeless operation 4 chn. Q mode + 4 chn. I mode Production run spring 2004 UMC 0.25  m technology Next Submission Oct. 20 th Production time ~9 weeks VME board design in parallel (Siena) Rectangle 5 x 5 mm 2 Reduce minimum sampling speed to 500 MHz (for DC) Daisy chain mode for N x 1024 bins Dual-channel for deadtimeless operation 4 chn. Q mode + 4 chn. I mode Production run spring 2004

DRS options Input Domino Wave Daisy-chain mode Input Readout Dual-channel mode

DRS (DAQ) Test Milestone AssemblyDesignManufactoring 2 nd Prototype Tests1 st Prototype Boards & ChipTest

DAQ System PMT Active Splitter ~7mto trigger (~20m) area monitor ~2m DRS Board (16chn) DCPre-Amp DRS Board (16chn) ~7m SIS VME crates optical fiber (~20m) Trigger Gigabit Ethernet Front-End PCs On-line farm Rack – PC (Linux) storage Fitted data: 10 Hz waveform data -> 1.2 MB/sec 90 Hz ADC / TDC data -> 0.9 MB/sec Raw data: 2880 channels 100 Hz 50% / 10% / 10% occupancy 2kB / waveform -> 5 x 25 MB/sec.

Waveform analysis Zero suppression in FPGA Single hit –ADC/TDC derived in FPGA Multiple hit –Waveform compressed in FPGA (2x12 bit -> 3 Byte) –Waveform fitted / compressed in PC cluster Store ADC/TDC only for “calibration” events Store (lossless) compressed waveforms for MEG candidates Zero suppression in FPGA Single hit –ADC/TDC derived in FPGA Multiple hit –Waveform compressed in FPGA (2x12 bit -> 3 Byte) –Waveform fitted / compressed in PC cluster Store ADC/TDC only for “calibration” events Store (lossless) compressed waveforms for MEG candidates Original Waveform Difference Of Samples Threshold in DOS Region for pedestal evaluation integration area ADC1/TDC1 ADC2/TDC2 T

ROOT for online analysis ROOT becomes more stable and is now widely used “Online extensions” are underway (life display of histos and N-tuples) Propose to use ROOT for online monitoring and single event display, CARROT for Web display For offline analysis, keep possibility to use ROOT or PAW ROOT becomes more stable and is now widely used “Online extensions” are underway (life display of histos and N-tuples) Propose to use ROOT for online monitoring and single event display, CARROT for Web display For offline analysis, keep possibility to use ROOT or PAW FE Analyzer *.mid ROOT GUI offline analysis ROOT *.root offline analysis HBOOK *.rz PAW ROOT online offline