ELN5622 Embedded Systems Class 7 Spring, 2003 Aaron Itskovich

Overview  Introduction –Definitions –Op Amps -- a quick review  Digital to analog conversions  Analog to digital conversions

Introduction to analog input and output  Physical phenomena are often analog in value -- they can take on a continuous range of values rather than discrete values –Examples include temperature, speed, position, pressure  For a microprocessor to operate on continuous physical values, conversion between analog and digital values is needed  Building blocks to perform the conversions are: –Digital to analog converters (DACs) –Analog to digital converters (ADCs)

Transducers Used to convert a process variable into an electrical signal or vice versa –Sensors Potentiometer (position) Strain gauge, piezoelectric device (force) Thermistor, thermocouple (temperature) Photoconductive cell, phototransistor (light) Current transformer, SENSEFET (current) Microphone (sound) –Actuators Solenoids, relays, speakers Darlington transistors, SCRs, thyristors

Signal conditioning  Most transducers output low-level signals –Usually less than 1V, may be millivolts or microvolts  Signal may also be noisy  Need to apply signal conditioning before A/D conversion –Amplification –Filtering –Linearization

Operational Amplifiers  Useful in the design of DACs and ADCs because of their performance characteristics –Open loop gain of several hundred thousand –Input current approximately 0, output impedance approximately zero

Digital to Analog conversion  Definitions –Offset: minimum analog voltage –Span: Maximum analog value - minimum analog value Common spans: 0-5 V, 0-10 V, 4-20 mA, +/- 5 V –Weight: analog change corresponding to a change in a bit position of the digital number (varies by bit position) –Step size: span / 2 n (n = # bits in code), weight of the LSB (also known as the resolution) –Example: Analog signal in range +5 to -5 volts, 8-bit digital number: Span = 10 volts Offset = -5 volts Step size = 10 / 256 = 39.1 mV Weights: 5, 2.5, 1.25,.625,

Digital to analog conversion  Function: take an n-bit digital input and output a corresponding analog voltage  DAC systems normally consist of three components: –An accurate reference voltage –The DAC itself –Op amp for output buffering  Ideal DAC would convert n-bit code B n-1... B1 B0 to output voltage as shown below –Vout = Span x ( B n B n B 0 2 -n ) + Offset –Vout will be a fractional value of the "full scale" voltage (span-offset) Maximum is the digital value of (all 1s)

Weighted resistor DACs  Weighted resistor DACs –Use an op amp and a current divider network to implement the conversion function

Interfacing DAC  In principle, any DAC can be interfaced to any microprocessor system  In practice, some combinations of DACs and microprocessors are easier than others and require much simpler hardware and software in the interface  Interfacing an 8-bit DAC to an 8-bit microprocessor is easy: –Write to port connected to DAC and signal DAC to begin  When DAC word > uP word, some problems can exist –How do we interface a 12-bit DAC to an 8-bit I/O bus without having glitches in the analog output? –Must use a double buffering scheme, as described in the text but best illustrated from [Sho87]

DAC & 68HC11 –No on-board D/A –Must use an external converter Ex. DAC0808 –8-bit D/A –Connect to a parallel I/O port

Analog to digital conversion  The function of ADCs is to quantize the analog voltage and then output the corresponding digital code value  As with the DAC conversion, a full-scale analog voltage will be divided into 2 n quantization levels or steps for an n- bit digital coding scheme  Slow approach -- counting conversion

Successive approximation  Successive approximation is a much faster method

The analog to digital subsystem in the 68HC11  The ADC system in the 68HC11 uses a variation of the successive approximation converter –DAC is replaced by a series of capacitors that are charged to the voltages that correspond to the weights of each bit Much like a capacitive ladder network –Capacitors are charged during a sample period then held during the approximation phase –Each capacitor starting with the one that corresponds to the MSB is switched in turn into the SAR circuit for the comparison process

Capacitor Ladder Network for A2D conversion in HC11

 68HC11 A/D –Supports 8 input ADC channels –Channels are located on port E Channel 0 on PE0 -- not available on EVBU due to use of jumper J2! Channel 1 on PE1, etc. –In performing A/D conversions, 4 conversions are performed as a "block," each taking 32 cycles cycles total –Control registers: OPTION ($1039) –ADPU and CSEL bits ADCTL ($1030) –Control and status information ADR1 - ADR4 ($ $1034) –Result registers

A2D operations on the HC11  To enable A/D operations on the HC11 –Enable the capacitor charging operations The system charge pump must be enabled at reset by setting the A/D power up bit (ADPU) in the system OPTION register This is used to charge the capacitors for the successive- approximation circuit Disabled by default to conserve power After enabling charge pump, the MCU should wait at least 100 usec before initiating A/D conversion –Allows capacitor voltages to stabilize

A2D operation on the HC11  To enable A/D operations on the HC11 –Select clock for successive-approximation register (SAR) circuitry A/D can use the E clock or an internal RC circuit –Use E clock if it is greater than 750 KHz (it is for the EVBU!) CSEL bit in OPTION register selects clock source (0 = E clock, 1 = RC circuit) –Must also apply high and low reference voltages (V RH and V RL ) to the chip that fixes span and offset -- 3 volt span is recommended minimum (VDD and VSS hardwired to the reference inputs on the EVBU)

A2D operation on the HC11  Single vs. continuous conversion –Single conversion HC11 performs one set of conversions and stops –Remember that one set is actually 4 conversions To select this, set the SCAN bit in ADCTL to 0 Writing to ADCTL initiates conversion –Also clears the CCF bit When conversion is complete, CCF bit is set –No interrupt, so you must poll Read data from ADR1-ADR4 To start another conversion, you must write to ADCTL again

A2D operation on the HC11 –Continuous conversion Set SCAN bit to 1 Writing to ADCTL initiates conversion –Also clears CCF CCF set after first block of 4 conversions is complete ADR1 - ADR4 continue to be updated –Round-robin fashion –Each register will be updated every 128 cycles (32 cycles for each conversion) When you read a register, value may be up to 128 cycles old

A2D operation on the HC11  Single channel vs. multiple channel –Single channel Channel is sampled 4 consecutive times and the resulting 4 conversions are placed into ADR1-4 –Each conversion takes 32 clock cycles Set MULT bit to 0 in ADCTL register Use CC, CB, and CA bits in ADCTL to select the channel to be converted –Always set CD to 0 (CD=1 is used for factory testing) Can use this with single or continuous conversion –Allows you to sample a single input every 32 cycles (62,500 samples per second with 2MHz E-clock)

A2D operation on the HC11 –Multiple channels Conversions for 4 channels will be performed Set the MULT bit in ADCTL to 1 Use bit CC of the ADCTL to specify which group of 4 channels is to be converted –CC = 0 -- inputs 0-3 in ADR1-4 –CC = 1 -- inputs 4-7 in ADR1-4 –CD should always be 0, CB and CA are don’t cares Can use this with single or continuous conversion –Each input is sampled every 128 clock cycles (15,625 samples per second)

Sumary Transducers –Signal conditioning –D/A conversion Must use external converter for HC11 –A/D conversion HC11 has built-in A/D converter –Uses port E –Can convert 8 channels –Operation: Enable charge pump, select clock source during initialization Select single or continuous conversion, single or multiple channels Initiate conversion by writing to ADCTL Wait for CCF flag to indicate conversion is complete Read results