Professor Jinyong (Andy) Chung Research Professor Department of Electrical Engineering Pohang University of Science and Technology, Pohang, Korea IWNE
Professor Jinyong (Andy) Chung Education BSEE, 1974, Seoul National University, Col lege of Engineering MSEE, 1976, Korea Advanced Institute of S cience and Technology IWNE
Professor Jinyong (Andy) Chung Current Interest Ultra Low Voltage/Low Power Circuit Des ign for SoC Applications High Speed Clocking/Signal Integrity System on Package DFT(Design for Testab ility) methodology development Nanotechnology Circuits IWNE
Professor Jinyong (Andy) Chung Work Experience 4/2003 ~presentPohang University of Science and Technology (Korea)Research Profess or Design for Testability on System in Package Low Voltage Circuits/Nano Circuits Design 9/1996 ~3/2003 Hynix Semiconductor Inc., Memory R&D (Korea) Senior Vice President, Chief Architect, Memory Products Design & Development 3/1992 ~ 8/1996 MOSEL-VITELIC Inc.(San Jose, CA) Director, DRAM Design Engineering 3/1987 ~ 2/1992 LG Semiconductor Inc., Semiconductor R&D (Korea) Director, Memory & System IC Design 3/1974 ~ 2/1987 (worked for following companies) VITELIC Corp (San Jose, CA), Synertek Inc.(San Jose, CA), National Semiconductor Inc(Sa nta Clara, CA), Western Digital Corp (Newport Beach, CA), Samsung Electronics, Ltd.(Kor ea) : Design Engineer / Design Section Manager / Design MTS Memory Products (SRAM /R OM /DRAM) & ASIC Products IWNE