CET 520/ Gannod1 The MIPS Architecture Section 2.12

CET 520/ Gannod2 Summary of Chapter  GPR with load-store architecture (better for pipelining) 2.3  Addressing modes supported should include displacement, immediate, and register indirect. 2.5  Support 8, 16, 32, and 64-bit integers and 64-bit floating point 2.7  Instructions should include load, store, add, subtract, move, shift 2.9  Flow control instructions should include comp eq, comp not eq, comp less, branch, jump, call, return 2.10  use fixed instruction encoding if interested in performance 2.11  provide at least 16 GP registers

CET 520/ Gannod3 MIPS overview load-store instruction set designed for pipelining efficiency fixed instruction set encoding efficient as a compiler target used in: –Nintendo 64 –laser printers from HP and lexmark –advanced set-top boxes from Motorola and Sony –The SGI POWER CHALLENGE is a shared-memory multiprocessor architecture based on the MIPS superscalar RISC R8000 chip

CET 520/ Gannod4 cont… –“…This simplicity makes the MIPS architecture a favorite choice among universities and colleges for their introduction to computer architecture classes. This simplicity also makes the MIPS architecture very attractive to the embedded microprocessor market as it enables very cost- effective implementations.” ( sierra.com/processors/history. html)

CET 520/ Gannod5 MIPS64/MIPS Registers 32 GPRs  R0..R31 Each holds a 64-bit (integer) value 32 FPRs  F0..F31 Each can hold a 64-bit (double-precision) or 32-bit (single-precision) value. R0 is always zero. A few special registers can be transferred to and from GPRs (e.g., fp status register) can move between FPR and GPR

CET 520/ Gannod6 Data Types byte (8-bits); hald-word (16- bits) word (32-bits) double (64- bit) integers single (32-bit) and double (64- bit) floating point integer operations assume 64- bits. if a smaller size is loaded into a register the upper portion of the register gets 0s or is sign extended.

CET 520/ Gannod7 Addresses and Addressing Modes The only data addressing modes are –immediate (16-bit immed) –displacement (16-bit offset) Register indirect is simulated by placing 0 in the displacement Absolute addressing is simulated by using R0 as the base register. Memory is byte addressable (64-bit addresses) a mode bit allows software to select either Big or Little Endian. All memory accesses must be aligned.

CET 520/ Gannod8 Instruction Formats R-format (R for register) I-format (I for immediate) op rs rt rd shamt funct 6 bits 5bits 5 bits 5 bits 5 bits 6 bits op rs rt address 6 bits 5bits 5 bits 16 bits J-format (J for jump) op target address 6 bits 26 bits

CET 520/ Gannod9 MIPS Instructions 4 classes of instructions: –loads/stores (memory access) –ALU operations –branches/jumps (flow control) –floating-point operations Load/Store all load/store instructions following same “format”: e.g., LD R1, 30(R2) load double register (load to/store from) displacement base register

CET 520/ Gannod10 Load/Store Instructions LDLoad Double LWLoad Word LBLoad Byte LBULoad Byte Unsigned LHLoad Half L.SLoad FP Single L.DLoad FP Double SDStore Double SWStore Word SHStore Half SBStore Byte S.SStore FP Single S.DStore FP Double

CET 520/ Gannod11 ALU Instructions Examples of MIPS ALU instructions –DADDU R1, R2, R3 –DADDIU R1 R2, #3 –LUI R1, #42 –DSLL R1, R2, #5 –DSLT R1, R2, R3 destination source 1source 2 immediate