Firmware based Array Sorter and Matlab testing suite Final Presentation August 2011 Elad Barzilay & Uri Natanzon Supervisor: Moshe Porian

Project Goals Building an integer array sorting Firmware on an FPGA. Building an integer array sorting Firmware on an FPGA. Develop a comprehensive MATLAB based testing and debugging environment. Develop a comprehensive MATLAB based testing and debugging environment.

Presentation Overview The need for sorting The need for sorting Project Overview Project Overview Implementation review Implementation review Sorting: Firmware Sorting: Firmware Test & debug: Software Test & debug: Software Communication: FW & SW Communication: FW & SW Results & demonstration Results & demonstration

The need for Sorting: Histograms as an example Many image processing algorithms relay on the use of histograms. For example - Photo “auto fix” – histogram equalization Photo Min Photo Max 0 Full Dynamic Range

For example:

Project Overview  System capabilities & requirements – Sorting an array of finite integers set. – Zero latency system. – Fully debug-able. – System operation and testing via PC interface.  Design principles – Generic implementation. – Top down design. – Error detection and handling.  System implementation on the DE2 evaluation card.  PC GUI implementation on MATLAB.  Complete development process: Characterization to operational platform.

High-level overview

SORT_TOP – Inputs Time Diagrams

SORT_TOP – Outputs Time Diagrams

SORT_TOP – Inputs & Outputs Time Diagrams Latency between input and output = 1 clock cycle

Bucket Sorting Problem: Zero-Latency requirement. allows only one system clock cycle between frame input and result output. Solution: use the Bucket-Sorting algorithm! Given the set of possible array elements, and elements order, Count repetitions for each element and output in order.

SORT_TOP

“Writing” block – DPR_update.vhd

“counters” block –DPR_block.vhd

“Reading” block - DPR_reader.vhd

DUDE – debug under development environment General scenario testing. Ability to generate errors and saving messages for error reproduction. Evolution parallel to the main FPGA project to test newly developed features and verify existing features.

“DUDE” – Debugging Under Development Environment MATLAB based GUI for data injection and result validation

“DUDE” – connection generation and main features Reloading last sent messages Serial port and CRC control Consecutive message sending: Random or GUI-screen generated messages.

“DUDE” – data generation Communications Error generation. UART Parity control Data table: generate, edit and view sent array. Repetitions counter All data generation is managed through the GUI!

“DUDE” – results viewer and verification The number table is the sorted array returned from the board. General status box to inform of the message status. If an error is identified at the board and an error notification message is returned this will be displayed here. The message box is also color indexed. View and compare the computer (ground-truth) results and the board generated values. Color indexing allows faster problem identification.

“DUDE” – implementation guidelines OOP based GUI. OOP based GUI. 2 main classes implemented: 2 main classes implemented: –CSettings – holds all the framework data and manages the messages list –CMessage – holds all the data per one given message and manages the dynamic data creation such as CRC and data length calculation. This modular design allows the GUI to be versatile and parameter independent. This modular design allows the GUI to be versatile and parameter independent. Easily adjustable to additional requested features. Easily adjustable to additional requested features.

PC – FPGA communication Serial communication - MATLAB API and designated FW blocks. MATLAB allows configuration of communication features. buffer overloading avoidance – Byte by Byte transmission.

Message Pack Structure SOF ID Data Length CRC EOF 8 bits 1 Byte. Some constant predefined flag 1 Byte. For message tracking 2 Bytes. Specifies the length of the data segment in bytes. 1 Byte. The CRC type will be defined later. 1 Byte. Some constant predefined flag Address 1 Byte. Specifies the addressed block Type 1 Byte. Type options are : set, query, sort [Data Length] X Bytes. (up to bytes) Holds the data and control signal to be fed into SORT_TOP DATA (payload)

Queuing system PC messages – bits/second Firmware clock – 60 MHz. – –Firmware is much faster… To allow testing of consecutive inputs a queuing system is required…

Queuing System - Overview

Data-path - Overview

Tested scenarios Sorting system: – –Basic test – random consecutive array. – –Constant arrays. – –Rising / Falling arrays. – –Fast toggling. – –Boundary values – zeros and 63’s in the array. Communication: – –CRC errors. – –EOF / SOF errors. – –UART parity error. – –Buffers overloading.

SignalTap – waveform Results First Frame incoming result Expected time diagram

Utilization Results

Timing Results

Demonstration…