1 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer Dr. Douglas J. Fouts LT Kendrick R. Macklin Daniel P. Zulaica Department of Electrical and Computer Engineering U.S. Naval Postgraduate School Monterey, California

2 of 23 Fouts MAPLD 2005/C117 Outline 1.High resolution imaging inverse synthetic aperture radar (ISAR). 2.Digital synthesis of realistic false target images. 3.The SRC-6E reconfigurable computer. 4.Synthesis of false target images on the SRC-6E. 5.Testing results. 6.Conclusions Synthesis of False Target Radar Images Using a Reconfigurable Computer

3 of 23 Fouts MAPLD 2005/C117 The USS Crockett, a typical target for a potential adversary. Synthesis of False Target Radar Images Using a Reconfigurable Computer

4 of 23 Fouts MAPLD 2005/C117 Target appearance on the screen of a typical surface search and navigation radar. Synthesis of False Target Radar Images Using a Reconfigurable Computer

5 of 23 Fouts MAPLD 2005/C117 Appearance of USS Crockett on U.S. Navy AN/APS-137 imaging Inverse Synthetic Aperture Radar (ISAR). Synthesis of False Target Radar Images Using a Reconfigurable Computer

6 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer Block diagram of electronic warfare system with false target image synthesis capability. Digital Image Synthesis Hardware

7 of 23 Fouts MAPLD 2005/C117 U.S. Navy Ship Range Bins Interrogating Radar Signal Reflected Radar Signal Synthesis of False Target Radar Images Using a Reconfigurable Computer Dividing a target into range bins.

8 of 23 Fouts MAPLD 2005/C117 Block diagram of digital image synthesis hardware. Synthesis of False Target Radar Images Using a Reconfigurable Computer

9 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer To synthesize a false target image, the math must be done very fast.

10 of 23 Fouts MAPLD 2005/C117 RTL diagram of Range Bin Processor Synthesis of False Target Radar Images Using a Reconfigurable Computer

11 of 23 Fouts MAPLD 2005/C117 The SRC-6E Reconfigurable Computer LINUX cluster of two PCs Each PC has –Two 1000 MHz Intel XEON® processors –Common memory –Snap port to Multi Adaptive Processor (MAP) Each MAP has –Two user-programmable Xilinx Virtex-II FPGAs (6 M gates each) –One Xilinx Virtex-II Control FPGA (not user programmable) –On-board memory –Snap port to PC –Two 96-bit wide chain ports to other MAP Programs written in C or Fortran. –User identifies which part(s) of program are converted to FPGA circuitry for (hopefully) increased execution speed –FPGA code can also be written in VHDL OR Verilog –FPGA can also be programmed schematically or with IP cores Synthesis of False Target Radar Images Using a Reconfigurable Computer

12 of 23 Fouts MAPLD 2005/C117 SRC-6E Architecture (half) Intel® μP L2 MIOC PCICommon Memory SNAPSNAP Controller On-Board Memory (24 MB) FPGA Intel® μP L2 μP Board FPGA 6x 800 MB/s MAP 315/195 MB/s (peak) Chain Port To/From Other MAP 800 MB/s Chain Port To/From Other MAP 800 MB/s Synthesis of False Target Radar Images Using a Reconfigurable Computer

13 of 23 Fouts MAPLD 2005/C117 MAP Software Development Code for FPGAs is isolated in external function SRC compiler translates C source code into FPGA programming file. MAP can also be programmed with Verilog, VHDL, IP cores, or schematically FPGA circuitry deeply pipelined with 100 MHz clock (10 ns period) Large pipeline fill time (large latency) Calls are inserted in the main program to –Initialize the MAP –Transfer input data from common memory to on-board memory –Call the external function –Transfer output data from on-board memory to common memory –Release the MAP (optional) Synthesis of False Target Radar Images Using a Reconfigurable Computer

14 of 23 Fouts MAPLD 2005/C117 Programming Steps Used in This Research Describe range bin processor using VHDL in the Aldec Active-HDL 5.2 environment –Code the individual logic blocks –Combine to build a single range bin processor –Instance the range bin processor the required number of times –Test code using Aldec Active-HDL simulator Create support and interface files for SRC-6E Create “main” part of program in C for execution on PCs in SRC-6E Compile and link Synthesis of False Target Radar Images Using a Reconfigurable Computer

15 of 23 Fouts MAPLD 2005/C117 Benchmarks 1.VHDL macro on the SRC-6E MAP 2.C program on the SRC-6E –1 GHz Xeon P3 –1.5 Gigabytes of RAM –Linux OS 3.C program on Pentium 4 system –3 GHz P4 –2 Gigabytes of RAM –Windows XP Professional OS Synthesis of False Target Radar Images Using a Reconfigurable Computer

16 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

17 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

18 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

19 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

20 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

21 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

22 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer

23 of 23 Fouts MAPLD 2005/C117 Conclusions 1.The SRC-6E compiler allows C programmers to utilize the MAP without having to become circuit designers. 2.Porting code to the MAP requires basic knowledge of the hardware. 3.Programming an SRC-6E requires less time and effort than developing FPGA designs using COTS FPGA development systems. 4.Overall performance of SRC-6E can be limited by transfer time between common memory and on-board memory. 5.Use of large data sets amortizes MAP overhead and pipeline latency across many calculations. 6.Applications performing a large number of calculations on each data set derive the largest performance boost from using the MAP. Synthesis of False Target Radar Images Using a Reconfigurable Computer