1 EECS 465: Digital Systems Lecture Notes # 8 Sequential Circuit (Finite-State Machine) Design SHANTANU DUTT Department of Electrical and Computer Engineering University of Illinois, Chicago Phone: (312) : URL:

2 Finite State Machine (FSM) Design FSMs are different from counters in the sense that they have external I/Ps, and state transitions are dependent on these I/Ps and the current state. Example : Problem Statement There is a bit-serial I/P line. Design an FSM that outputs a ‘0’ if an even # of 1’s have been received on the I/P line and the outputs a ‘1’ otherwise. When do we need an FSM (i.e., seq ckt) to solve a problem rather than a combinational ckt? Ans: When the problem requires the design to remember something about past inputs in order to solve the problem Note : If a +ve edge triggerred synchronous sequential circuit is being designed, the counting of the # of 1s (i.e., the sampling of the input(s), for a general FSM) essentially occurs T logic +T setup time before every +ve edge. FSM xO/p y CLK x # of 1s even (0) odd (1) even (2) odd (3) odd (3) T logic + T setup Sampling instances

Approach to determining states of an FSM (mainly a “pattern”-recognition FSM [string, mathematical, etc. patterns] as opposed to an “action” FSM): First determine the min # of useful information classes about past i/ps required to solve the problem (requires analytical thinking about the problem) Each info class  a potential state From this 1 st cut at possible states, determine if there are well-defined transitions from each state for all possible i/p values. If so then these states can be the final states; otherwise some states may need to be refined into multiple states to achieve well-defined transitions (see FSM word prob. 1). In this problem, only 2 classes of information are reqd: whether an even # of 1s have been received so far, or an odd # of 1s have been received so far & there are well-defined transitions between them. Thus these 2 classes become 2 states. Solution 1: (Mealy) 0/0 Even Odd 1/1 1/0 0/1 Reset Output Input Transition Arc O/P is dependent on current state and input in Mealy Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse). 0 Even Reset [0] Odd [1] Output Input Output is dependent only on current state Solution 2: (Moore) Moore Machine: Output is associated with the state and hence appears after the state transition takes place.

4 Determining a Reset State: A reset state is a state the the FSM (seq ckt) should be in when it is just powered on. In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps Based on the above definition, decide if any of the states determined so far can be a reset state (i.e., its defn. is consistent w/ not having received any i/p). E.g., in the parity detector problem, the even state qualifies to be the reset state, as in the reset state no i/ps recvd  zero 1’s recvd  even # of 1’s recvd  it can be the even state If not, then need to have a separate reset state, and have the correct transitions from this state to the other states (depending on the problem solved by the FSM). Solution 1: (Mealy) 0/0 Even Odd 1/1 1/0 0/1 Reset 0 Even Reset [0] Odd [1] Output Input Output Input Transition Arc Output is dependent only on current state O/P is dependent on current state and input in Mealy Solution 2: (Moore) Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse). Moore Machine: Output is associated with the state and hence appears after the state transition take place.

5 FFs External I/Ps External O/Ps m1m1 m2m2 nn Comb. Logic CLK FFs n CLK n Output Logic m2m2 Next State Comb. Logic m1m1 External I/Ps External Outputs Mealy Machine Model Moore Machine Model even  odd Time t : Even I/P  = propagation delay of logic of Mealy M/C t t+  t+T CLK t+T CLK +  2 state = Even x=1 O/P=0 O/P=1 (Mealy) state = Odd Moore O/P=1  2 = propagation delay of O/P logic unit of Moore M/C

6 State Transition Table (Even-Parity Checker) Encoding: State Variable A, Even State: A = 0 ; Odd State: A = 1. Q FF N.S. & O/P Logic CLK x y2y2 ADADA Or FFs y1y1 N.S. Logic O/P Logic DADA A Q x D A = A  x ; T A = x y 1 = A for Moore y 2 = A  x for Mealy A x A + y 1 y 2 D A T A Present State Input Next State Moore O/P Mealy O/P D-FF Excit. T-FF Excit. Input variables to comb. logic Output functions Q Q + D Q Q + T Excitation tables for a D-FF and a T-FF Mealy and Moore Seq. Circuit Models

7 State=0 Even State=1 Odd 1/1 1/0 0/1 Reset0 State=0 Even Reset [0] State=1 Odd [1] x FF N.S. Logic CLK Q QD D- Mealy Moore Assume single bit state information stored in a D-FF CLK x D Q (state) y 2 (Mealy O/P) y 1 Moore O/P) State Transition is occurring State Transition is occurring S.T. is complete. odd even oddeven 0/0

Moore M/C Implementation D Q Q R CLK y1y1 x=1 A 0 a) D-FF T Q Q R A y 2 x CLK b) T-FF Moore O/P is synchronized with clock. Reset D A = A  x ; T A = x y 1 = A for Moore; y 2 = A  x for Mealy 8 Mealy M/C Implementation D Q Q R CLK y1y1 x=1 A 0 1 T Q Q R x CLK y1y1 a) D-FF b) T-FF Mealy O/P is not synchronized with clock. Reset Note: Here Moore and Mealy state transition functions are the same. This will not always be the case.

9 Difference Between Mealy and Moore Machine Mealy Moore (1) O/Ps depend on the present O/Ps depend only on the state and present I/Ps present state (2) The O/P changes asyn Since the O/Ps change -chronously with the when the state changes, enabling clock edge and the state change is synchronous with the enabling clock edge, O/Ps change synchronously with this clock edge (3) A counter is not a Mealy A counter is a Moore machine machine (o/ps = state bits) (4) A Mealy machine will have the same # or fewer states than a Moore machine

Transformations Between Mealy and Moore FSMs 10 B D C 00,10 / 01 11/01 A 01/01 i/ps o/ps B D [01] C 00,10 11 A 01 i/ps o/ps Mealy  Moore (no extra states needed) As can be seen, Mealy  Moore transformation can result in extra states: Mealy states w/ different o/ps in their input transition arcs will need to be replicated in a Moore FSM, w/ the # of replications = # of different o/ps in the input transitions associated w/ the Mealy state However, a transformation from Moore  Mealy, will not require any extra state: Each Moore state becomes a Mealy state w/ its o/p indication moving from the state to all its input transition arcs B D C 00,10 / 00 11/01 A 01/11 i/ps o/ps Mealy  Moore (extra states needed) B D1 [00] C 00,10 11 A 01 i/ps o/ps D2 [11] D3 [01]

11 Another example: A simple vending machine Here is how the control is supposed to work. The vending machine delivers a package of gum after it has received 15 cents in coins. The machine has a single coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor indicates to the control whether a dime or a nickel has been inserted into the coin slot. The controller’s output causes a single package of gum to be released down a chute to the customer. One further specification: We will design our machine so it does not give change. A customer who pays with two dimes is out 5 cents! Vending Machine FSM CLK Reset Coin Sensor Gum Release Mechanism Open Vending Machine block diagram 0C  15C 10C5C5C States:

12 — The figure below show the Moore and Mealy machine state transition diagrams. 0 cent [0] 5 cent [0] 10 cent [0] >=15 cent [1] Moore machine >=15 cent 10 cent 5 cent 0 cent Mealy machine Moore and Mealy machine state diagrams for the vending machine FSM Reset / 0 Reset Reset / 0 N / 0 D / 0 N / 0 N+D/1 N+D N D N D D/1 Reset )/0 Reset )/0 Reset Reset / 1

13 Q 1 Q 0 D N Q 1 + Q 0 + Open Open x x x x x x x x x x x x x x x x Present State Inputs Next State Moore Output Mealy Output Q + = D Q Q + D —State transition table for Moore and Mealy M/C (next state col. also gives D-FF excitation). Encoded vending machine state transition table. Note: Do not have to design for the reset input if FFs have a direct reset inputs. Make sure though that reset state is encoded as all 0’s if possible; otherwise need FFS w/ asynch. reset as well as set inputs

14 Implementation using D-FFs Q1Q0Q1Q0 DN Q1Q0Q1Q0 DN Q1Q0Q1Q0 DN x x x x x x K-map for D 1 K-map for D 0 K-map for Open (Moore) D 1 = Q 1 + D + Q 0 ·N OPEN = Q 1 ·Q 0 OPEN = Q1·Q 0 + D·Q 0 + D·Q 1 + N·Q 1 Moore Mealy Q1Q0Q1Q0 DN x x K-map for Open (Mealy)

15 D Q Q R Q R Q0Q0 N N Q0Q0 Q1Q1 N Q1Q1 D D0D0 D1D1 Q1Q1 OPEN D CLK Vending machine FSM implementation based on D flip-flops(Moore). Q1Q1 Q0Q0 Similarly, a Mealy implementation; only the OPEN function changes. Reset Input transition logic cost = 17 (total gate i/ps)

16 Implementation using J-K FFS Q 1 Q 0 D N Q 1 + Q 0 + J 1 K 1 J 0 K x 0 x x 1 x x 0 x 1 1 x x x x x x x x x x x x x x x x x x x 0 0 x x 0 1 x x 0 1 x 1 1 x x x x x x x 0 x x 0 x x 0 x x x x x x x Remapped next-state functions for the vending machine example. Q Q + J K x x 1 0 x x 0 J-K Excitation

Q1Q0Q1Q0 DN Q1Q0Q1Q0 DN Q1Q0Q1Q0 DN Q1Q0Q1Q0 DN 0 0 x x 0 1 x x x x 1 1 x x x x 0 0 x x x x x x 0 1 x x 1 x x 0 x x 1 x 0 0 x x 1 0 x x x x 0 0 x K-map for J 1 K-map for K 1 K-map for J 0 K-map for K 0 K-maps for J-K flip-flop implementation of vending machine. J 1 = D + Q 0 ·N K 1 = 0

18 J Q Q R Q1Q1 CLK K J Q Q R Q0Q0 CLK K OPEN N Q0Q0 D N D Q1Q1 N J-K flip-flop implementation for the vending machine example (Moore). Similarly, a Mealy implementation; only the OPEN function changes. Reset Input transition logic cost = 12 (total gate i/ps), much less than using D-FFs (17) due to the numerous X’s in the excitation function of a J-K that combinational logic synthesis can use to minimize function cost

19 Basic Steps in the FSM Design Procedure (1-3 mainly for pattern-recognition FSMs) 1. Understand the problem and determine the minimal # of different information classes about past i/ps required to solve it. 2. Convert these information classes into distinct states (which we informally call tentative states), and determine the state transition diagram of the FSM. 3. If the state transitions between states are well-defined (i.e., for each state and i/p value, it is unambiguous what the next state should be), then these are the final states. Otherwise, states from which transitions are not well defined need to be broken into multiple states (called extra states) so that non-well-defined transitions are then translated to well-defined transitions between the original state(s) that did not have all transitions well-defined, and the extra state(s), and also from the extra state(s) to other original states (see, e.g., FSM prob. 1 next) 4. Determine the reset state 5. Perform state minimization 6. Encode states in binary [optional—perform state assignment for logic minimization], and obtain state transition table and FF excitation for desired FF type. 7. Minimize the FF input functions (using K-Maps or QM, for example) and implement the FSM using these FFs and logic gates (or MUXes, PLAs, PALs, etc.) that implement the FF’s input functions.

20 FSM Word Problem 1: Design a system that outputs a ‘1’ whenever it receives a multiple of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x. — Relevant information classes needed to solve the problem: (A) A multiple of 3 # is received. (B) A non-multiple of 3 # is received. Questions to consider: (1) How do we go from (A)  (B) Ans.: If a ‘1’ is received (2) How do we go from (B)  (A) Ans.: Not clear. Need to split up (B) further into (B1): 3y+1 # of 1’s received. (B2): 3y+2 # of 1’s received. Where y is an integer  0.

21 Note: (A): is 3y+0 = 3y # of 1’s received. Now the transitions between the3 classes of information is clear: (A)  (B1)  (B2)  (A) 1 received Hence these classes of information can be considered states of the required as states of the required FSM: These 3 states can be represented by 3y+I, i = 0,1,2 i=0 i=1 i=2 [0] i=1 [0] i=0 [1] Reset 0/1 0/0 1/0 1/ Moore MachineMealy Machine Input Output 1/0

22 FSM Word Problem 2: Design a system that outputs a ‘1’ whenever it receives: (a) A multiple of 3 # of 1’s AND (b) A non-zero even # of 0’s E.g., ((0,2), (3,2), (3,4), (6,2),···) — Relevant classes of information: Use D&C to figure this out! - Break problem into relevant classes of # of 1’s & relevant classes of # of 0’s - For # of 1’s: 3y+i, i = 0,1,2 [3 classes] - For # of 0’s: 2z+j, j = 0,1 For j = 0, we need to distinguish between zero (z = 0) and non-zero (z > 0) # of 0’s - Thus we have 3 classes: 2z+0, z = 0 ( 0 ) 2z+0, z > 0 ( non-zero even ) 2z+1 ( odd ) # of 0’s # of 1’s

23 The relevant # of 1’s can be represented by i = { 0, 1, 2 } ( # of 1’s = 3y+i ) — The relevant # of 0’s can be represented by j= { 0 0, 0 >0, 1 } ( # of 0’s = 2z+j ) where the subscript of the 0 indicates whether z=0 or z>0. — Since at any point time, a certain # of 1’s and # of 0’s will have been received, the state of the system will be given by a combination of relevant # of 1’s and # of 0’s. — There are 9 combinations: { 0, 1, 2, } X { 0 0, 0 >0, 1 } =  (0,0 0 ), (0,0 >0 ), (0,1), (1,0 0 ), (1,0 >0 ), (1,1), (2,0 0 ), (2,0 >0 ), (2,1)  # of 1’s # of 0’s Cartesian Product

24 (0,0 0 ) (1,0 0 ) (0,0 >0 ) (2,0 0 ) (2,1) (1,1) (0,1) (2,0 >0 ) (1,0 >0 )

25 (0,0 0 ) (1,0 0 ) (0,0 >0 ) (2,0 0 ) (2,1) (1,1) (0,1) (2,0 >0 ) (1,0 >0 ) Reset Note: 0 >0  2z+j, j = 0 z > 0 1/0 0/0 1/0 0/0 0/1 1/0 0/0 1/0 1/1 1/0

26 Interacting FSMs i=2 [0] i=1 [0] i=0 [1] Reset j=0 z>0 [1] j=1 [0] j=0 z=0 [0] Reset For # of 1’s: 3y+i, i = 0,1,2 [3 classes]: FSM1 For # of 0’s: 2z+j, j = 0,1 For j = 0, we need to distinguish between zero (z = 0) & non-zero (z > 0) # of 0’s [3 classes]: FSM2 Another option is to have 2 independent FSM’s one for detecting the desired # of 1’s and another for the desired # of 0’s. The o/p of the combined machine is 1 when both FSM’s are in states w/ o/p = 1 FSM2 AND x y o/p1o/p2 FSM1 1 state pair Do we save on FFs here? What about the general case (in which we divide an FSM w/ m1*m2 states into 2 FSMs, one w/ m1 and the 2 nd w/ m2 states ? Do we save on logic (here and in general)? Each pair of states of the 2 FSMs  a state of the composite fsm (previous design)

27 Interacting FSMs (contd) i=2 [0] i=1 [0] i=0 [1] Reset j=0 z>0 [1] j=1 [0] j=0 z=0 [0] Reset FSM2 AND x y o/p1o/p2 FSM1 a state pair Each pair of states of the 2 FSMs  a state of the composite fsm (previous design) Q: When can a single FSM design be decomposed into >= 2 simpler interacting fsm’s? A: When the compound o/p condition can be decomposed into multiple smaller o/p conditions joined together by some logical operations (as in this example). In such a case, these smaller conditions can each be determined by a simpler fsm. Each of these simpler fsm’s o/ps are used to determine the final o/p via extra logic depending on how the multiple smaller o/p conditions are logically “connected” to form the original o/p condition. 0