Silicon – On - Insulator (SOI)

SOI is a very attractive technology for large volume integrated circuit production and is particularly good for low – voltage, low power and high speed digital systems

Advantages of SOI technology over bulk technology SOI wafers potentially offer: Perfect transistor isolation Higher packaging density Reduced parasitic drain capacitance

Advantages of SOI technology over CMOS technology Excellent lateral and vertical isolation of active devices from substrate eliminating inter-device leakage and latch-up in CMOS devices Effective reduction of substrate coupling, allowing higher quality inductors with increased Q factor Effective reduction of interference and cross talk between mixed signal devices Reduced soft errors from radiation (electron – hole pair generation)

Faster device operation due to reduced parasitic capacitance Lower power consumption due to lower operating voltages Reduced die area per function – reduced area required for lateral junction isolation, resulting from the absence of wells and the possibility of the possible direct contact of the source and drain diodes in the NMOS and PMOS transistors

Performance improvement equivalent to the next technology node without scaling Potential to simplify device fabrication steps fewer mask and ion implantation steps, due to the elimination of wells Less complex lithography and etching required to achieve next generation performance

SOI structure

SOI applications This can be segmented into three categories depending on the BOX layer as  Thick BOX layer wafers  Thin BOX layer wafers  Ultra thin BOX layer wafers

Thick BOX layer wafers Si layer thicker than one micron – 1000nm Power switching devices High speed bipolar devices MEMS i.Military ii.Aerospace iii.Industrial

Thin BOX layer wafers CMOS IC applications i.PDA / Hand sets ii.Mainframes iii.Portable wireless devices iv.Automotive v.Workstations

Ultra thin BOX layer wafers 0.1 micron CMOS fabrication i.High end PC ii.Servers

SOI challenges Cost Continuity and thickness uniformity of the BOX layer Defects like voids and inclusions in BOX SOI CMOS devices exhibit parasitic phenomenon Floating body effects Self heating effects - due to thermal insulation of the device from the substrate by the BOX layer Floating body leading to increased D-S leakage currents

Types of SOI wafers PDSOI – silicon surface layer is thicker than the depth of the depletion region in the transistor’s channel FDSOI - silicon surface layer is equal to the depth of the depletion region in the transistor’s channel

This also depends on the silicon layer thickness above the BOX layer and the doping concentration in the channel FDSOI – channel doping concentration is low enough such that the gate depletion region extends throughout the entire thickness

Si surface layer thicker than 200nm – PDSOI Si surface layer thickness reduced to about 100nm - FDSOI The depletion layer of PDSOI does not reach through the entire silicon channel / body region PD material usually has a Si thickness greater than 0.15μm For FD devices, the SOI film is thinner than the device depletion width In FDSOI, there is no body region of the MOS device that can be charged, hence no floation body

SOI fabrication

Separation by Implantation

Smart Cut Implant with hydrogen and anneal Oxidized, annealed Flip implanted wafer onto substrate and bond the wafers Split wafer along the stress fracture Polish

Smart cut - unibond

Grind and etch back process

Epitaxial Layer transfer (Eltran)