Lecture 17 Lecture 17: Platform-Based Design and IP ECE 412: Microcomputer Laboratory

Lecture 17 Outline Platform-based Design Various IPs (intellectual property) Design Domains and Levels of Abstractions

Lecture 17 Review Questions 1.What are Observability and Controllability? Name one way to improve both. –Observability: ease of observing a node by watching external output pins of the chip –Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip –Scan chain 2.Name some testing types. –Dynamic vs. Static i.e. simulation vs. formal methods –Deterministic vs. Random Pre-specified vs. randomly generated sequence of inputs –Waveforms/logs checking vs. self-checking Non-automatic vs. automatic testing –Black- vs. glass-box testing Considering only specification vs. considering implementation in designing tests –Unit vs. integration testing Module vs. System testing

Lecture 17 Platform-based Design Platform Based Design is an organized method to reduce the time required and risk involved in designing and verifying a complex SoC, by heavy reuse of combinations of hardware and software IP. Rather than looking at IP reuse in a block by block manner, platform-based design aggregates groups of components into a reusable platform architecture.

Lecture 17 Platform Alternatives

Lecture 17 Promises of Platform-based Design It is the next logical step in IP reuse, moving up from ad hoc block reuse to the reuse of aggregates of IP blocks and an integration architecture –reduce design effort and risk –improve time to market Rapid design derivatives become possible –allowing optimization and tailoring of products to very specific application needs and markets Platforms are a way of capturing and reusing the best architectures and design approaches –in general, there are only a few optimal architectures for particular application domains –platforms serve as transmission mechanism from more experienced design teams and architects to less experienced designers

Lecture 17 Intellectual Property (IP) Building block components (roughly equivalent terms) –Macros, cores, IPs, virtual components (VCs) Examples –Microprocessor core, A/D converter, Digital filter, Audio compression algorithm Three types of IP blocks –Hard (least flexible) –Firm –Soft (most flexible)

Lecture 17 Hard IP Delivered in physical form (e.g., GDSII file) Fully –Designed –Placed and routed –Characterized for timing, power, etc. Tied to a manufacturing process –Actual physical layout –Fixed shape Complete characterization –Guaranteed performance –Known area, power, speed, etc. No flexibility

Lecture 17 Fixed Schematics and Layout Ground Power A-Input B-Input Data Out Hard Macros Schematic of a NAND gateLayout of a NOR gate

Lecture 17 Hard IP Examples and Constraints A microprocessor core –PowerPC, ARM AMS (analog/mixed-signal) blocks –ADC, DAC, filter A phase-locked loop (PLL) A memory block design Features –Deeply process dependent –Stricter performance requirements –Electrical constraints, such as capacitance, resistance, and inductance ranges –Geometric constraints, such as symmetry, dimension, pin location, etc. –Need to provide interface for functional and timing verification

Lecture 17 Soft IP Delivered as synthesizable RTL HDL code (e.g., VHDL or Verilog) Performance is synthesis and process dependent Synthesizable Verilog/VHDL Synthesis scripts, timing constraints Scripts for testing issues –Scan insertion, ATPG (automatic test pattern generation), etc.

Lecture 17 Some Soft IPs Counter, Comparator, Arithmetic/Logic Unit PCI bridge Microprocessor core –Representation form less process dependent –Final performance is still process and synthesis dependent

Lecture 17 Firm IP Blocks Intermediate form between hard and soft IP –Some physical design info to supplement RTL –RTL or netlist or mixture of both –More (or less) detailed placement –Limited use beyond specified foundry

Lecture 17 Understand IPs The quality of IPs and support will be the key to the success of the IP business Need to pay much attention on software IP issues Need application and system design expertise Core-based design is effective on IP/core integration Need to develop a combining platform- and core- based design methodology/environment for system designs

Lecture 17 Designers’ Technical Concerns on IP Reuse Is the IP source (provider) reliable? How can I make sure the functional correctness of the IP? How much effort do I have to invest in test-bench development for design verification with reused IP? What if I need to modify part of IP design? What if the final timing is not satisfied due to the IP? What ’ s the risk of the design project due to any possible defect caused by the IP? What ’ s the worst scenario when reusing the IP and what are the damage control plan?

Lecture 17 SoC Design Domains Represent different aspects of a system –System or behavioral domain –Structural or RTL domain –Physical domain System Behavior Structural RTL Physical Design

Lecture 17 Architectural Abstraction Level Logic Abstraction Level Circuit Abstraction Level Behavioral (System) Domain Applications Operating Systems User Programs Subroutines Instructions Adders, gates, flip-flops Structural (RTL) Domain Computer Microprocessor Transistors The Y Chart Physical Domain Chips, Boards, Boxes Modules Cells Transistors

Behavioral Domain What a particular system does Functionality User interface Applications Operating system Subroutines, etc…

Structural Domain How entities are interconnected to implement prescribed behavior Logic gates Registers RISC processor, etc…

Lecture 17 Physical Domain Physical structures to implement behavior Devices (transistors) Interconnections (wires) Physical qualities: conductivity, capacitance, etc.

Lecture 17 The Adder Example An n-bit adder –Adds two n-bit numbers A and B to produce a result C

Lecture 17 Behavioral Representation How a design responds to a set of inputs? Specification of behavior –Boolean equations –HDL, e.g., Verilog or VHDL

Lecture 17 Example: 1-bit Adder (cont’) Boolean equations Verilog Sum = A.B’.C’ + A’.B’.C + A’.B.C’ + A.B.C Carry = A.B + A.C + B.C module carry (co, a, b, c); output co; input a, b, c; assign co = (a&b) | (b&c) | (a&c); endmodule

Lecture 17 Structural Representation How components are interconnected to perform the required function Specification –Typically a list of modules and their interconnections

Lecture 17 Example: 4-bit Adder (cont’)

Lecture 17 module Add4 (S, c4, ci, a, b); input [3:0] a, b; input ci; output [3:0] s; output c4; wire [2:0] co; add a0(co[0],s[0],a[0],b[0],ci ); add a1(co[1],s[1],a[1],b[1],co[0]); add a2(co[2],s[2],a[2],b[2],co[1]); add a3(c4, s[3],a[3],b[3],co[2]); endmodule modules interconnections module add (co, s, a, b, c); input a, b, c; output s, co; // describe 1-bit adder enddmodule Structure Description in Verilog

Lecture 17 Physical Representation How to build a part to guarantee specific structure/behavior Physical specifications –Materials qualities Resistance, capacitance, etc. –Photo-masks required by various fabrication steps

Lecture 17 Physical View of the Adder

Lecture 17 Next Time Case studies of SoC in FPGAs