Eunil Won/Korea U1 Vertex/Tracker summary Jul Eunil Won/Korea University

Eunil Won/Korea U2 Vertex/Tracking Summary Probably I am not the right person to summarize... There were 5 talks during the workshop - 1 vertex, 2 TPC, 2 Silicon tracking R&D status of FPCCD vertex detector GEM TPC beam test result Micromegas TPC beam test result Silicon tracking for ILC (for SiLC) DSSD R&D Status first (serious) beam test results with B on

Eunil Won/Korea U3 Fine Pixel CCD (FPCCD) by Y. Sugimoto (KEK) Accumulate hit signals for one train and read out between tr ains (Other options read out 20 times per train) Fine pixel of ~5  m (x20 more pixels than “standard” pixels) t o keep low pixel occupancy Fully depleted epitaxial layer to minimize the number of hit pi xels due to charge spread by diffusion Two layers in proximity make a doublet (super layer) to mini mize the wrong-tracking probability due to multiple scatterin g Tracking capability with single layer using cluster shape can help background rejection Three doublets (6 CCD layers) make the detector Operation at low temperature to keep dark current negligible (r.o. cycle=200ms)

Eunil Won/Korea U4 Baseline design 3 super-layers (three doublets) - 6 single layers grouped in three radial positions - R = 20,22,39,41,58,60 mm - thickness = 80  m/layer - position resolution = 2  m

Eunil Won/Korea U5 Tracking efficiency cos  p mis d=10mm,  =40/mm 2 d=2mm,  =40/mm 2 d=10mm,  =2/mm 2 Mis-identification Probability (p=1 GeV/c,t Si =50  m) Expected hit density 40/mm 2 /train (TESLA) 20/mm 2 /train (Nominal) 15/mm 2 /train (LowQ) at R=20 mm, B=3 T Double structure helps in reducing mis-identification probability !  : background hit density

Eunil Won/Korea U6 Impact parameter resolution p=1, 3, 5, 10, 20, 50, 100 GeV/c T. Nagamine Old standard conf. R=24,36,48,60 mm t = 330  m/layer  = 4  m FPCCD configuration R= 20, 22, 39, 41, 58, 60 mm t = 80  m/layer  = 2  m

Eunil Won/Korea U7 Lorentz angle Lorentz angle in depleted-layer –tan  =  n B  n : electron mobility –Carrier velocity saturates at hi gh E field: –  n =0.07 m 2 E=1x10 4 V/cm –  n =0.045 m 2 E=2x10 4 V/cm –Small angle can be cancelled b y tilting the wafer May not be a serious problem –Number of hit pixels does not i ncrease so much B=3TB=5T E=1x10 4 V/cm  =12deg  =19deg E=2x10 4 V/cm  =7.7deg  =13deg

Eunil Won/Korea U8 Lorentz angle Calculation of E-field in epi-layer –Tools FEMLAB (COMSOL in Japan) 3.1 Solve Poisson equation by finite element analysis (FEA) –Parameters Material is assumed fully depleted (No free charge) n-layer: N D =1x10 16 /cm 3 =1.6x10 3 C/m 3 Epi-layer: N A =1x10 13 /cm 3 =-1.6 C/m 3 V G =4 V t SiO2 =100 nm t n =1  m t epi =15  m

Eunil Won/Korea U9 Lorentz angle – Almost constant E-field of ~10 4 V/cm in epi-layer can be achieved –E-field in epi-layer depends on gate voltage Higher (positive) gate voltage gives higher E-field Positive gate voltage should be applied during train crossing in order to get saturated carrier velocity and less Lorentz angle (Inverted (MPP) mode can be maintained for ~1ms) –The Lorentz angle of 12 degrees is expected at B=3T Result of E-field calculation - Summary Electric Potential

Eunil Won/Korea U10 TPC reports (two talks) In the TPC R&D, one of major issues is the readout scheme There are three readout schemes for LC-TPC in the market “Ultimate” MWPC : (well established  fall back option) 1 mm thin gap between anode-wires to cathode-pad 2 mm small pitched anode-wires Gas Electron Multiplier (GEM) Narrow pad response function & fast signal (  t~ 20ns) only electrons are collected by the readout structure High flexibility in the geometry of the readout pads Micro Mesh Gaseous Structure (MicroMEGAS) Micromesh supported by μm - high insulating pillars Direct detection of avalanche electrons K. Ikematsu (DESY) H.Kuroiwa (Hiroshima Univ.) Beam test on Apr 05 (KEK) Beam test on Jun 05 (KEK)

Eunil Won/Korea U11 GEM

Eunil Won/Korea U12 GEM

Eunil Won/Korea U13 GEM

Eunil Won/Korea U14 GEM

Eunil Won/Korea U15 GEM

Eunil Won/Korea U16 GEM

Eunil Won/Korea U17 GEM

Eunil Won/Korea U18 GEM

Eunil Won/Korea U19 GEM

Eunil Won/Korea U20 Micromegas Micromesh supported by μm - high insulating pillars Multiplication takes place between th e anode and the mesh One stage Direct detection of avalanche electro ns –Small E×B effect –Fast signals –Self-suppression of positive ion feedback (ions return to the grid) –Better spatial resolution –No wire angular effect 50μm S1 S2  Micromegas

Eunil Won/Korea U21 TPC Length of FC : 26 cm Pad – 2×6 mm, 0.3mm gap – 32 pads×12 pad rows ⇒ 384 readout channels – Non-staggered – Pad plane : 10×10cm Readout –ALEPH TPC electronics 24 amplifiers, 16 channels each 500ns shaping time, charge sensitive sampled every 80 ns digitized by 6 TPDs Micromegas

Eunil Won/Korea U22 X Resolution as a function of Z C d fixed for each B Row6 + Row7 C d = C d (PRF) Preliminary results Micromegas

Eunil Won/Korea U23 Z Resolution as a function of Z σ z ⋍ 500μm at 0.5T B = 0T B = 1T B = 0.5T Unlike σ X, σ Z has no significant B-dependence Preliminary results Micromegas

Eunil Won/Korea U24 Summary To measure Micromegas TPC performance –We did the beam test at KEK-PS π2 beam line us ing 4GeV neg. pions in magnetic field –Micromegas in TPC worked stably Measured diffusion constants are consistent with Mag. simulation σ x ⋍ 200μm, σ z ⋍ 800μm at 1T –But these results are still very preliminary Micromegas

Eunil Won/Korea U25 Comparison btw GEM and MicroMegas by me... ReadoutMWPCGEMMicroMEGAS gasTDR P5 Ar + isobutane (95:5)  PR (0) 1.39 mm (1T) 423  m (1T) 506  m (1T) 800  m (*) (1T) CDCD 208  m/cm 1/2 169  m/cm 1/2 188  m/cm 1/2 ZZ < 500  260 mm < 400  260 mm ~800  260 mm (*) see the figure 2 track resolution track-cluster matching It may not be fair comparison as MicroMEGAS beam test finished just before (June)

Eunil Won/Korea U26 SiLC (Silicon tracking for the International Linear Collider) H.J.Kim (KyungPook National U.) on behalf of the SILC R&D Collaboration (major transpariencies from Aurore Savoy-Navarro) SiLC by H.J. Kim

Eunil Won/Korea U27 First Prototype on Si strips of different length VA64_hdr Tsh=3.7µs 28cm x N=1,4 Built by Geneva U., ETH Zurich & Paris with AMS technique Courtesy G.Ambrosi (Perrugia) ‘’Serpentine technique’’ recto/verso SiLC

Eunil Won/Korea U28 Signal over noise as a function of strip length Signal spectrum is summed over a cluster after pedestal and common mode subtraction. The radioactive source is a Sr90-Y90 beta source. The S/N measurements were achieved on variable length strips with the prototype at Paris test bench sensor to be measured Results see next slide SiLC

Eunil Won/Korea U29 Results on S/N Collaboration Paris-Prague New 20 L=28cm, S/N(MPV)=20 or S/N(Mean)=30 L=56cm, S/N(MPV)=12 or S/N(Mean)=18 Cluster size~2 Noise vs capa Next steps: Change detector & FE prototypes go to test beam SiLC

Eunil Won/Korea U30 Some other S/N measurements and/or computations Nomad experiment: results from beam tests on S/N with same sensors and VA1 FE chips These results and the ones we have obtained are confirming that 30 cm long strips have S/N greater than 20, and 60 cm long strips have S/N greater than 10. Nota bene: These results are of course dependent of the detector prototype and the associated F.E.E. Curve computed with the known parameters of VA_64hdr SiLC

Eunil Won/Korea U31 2) Development of fabrication line for new sensors Several Institutions in SILC (also Helsinki U.) are developing new sensor research lines Such facilities are very usefull for developing & testing new ideas and transfer to Industry. For large production, high quality and reliability: HAMAMATSU Monopoly Ex1: 5’’ DSSD fab. line in Korean U. Ex2: rad hard sensor techno at IMB-CNM J.Lee’s talk SiLC

Eunil Won/Korea U32 R&D on Electronics The Si tracking system: a few 100m 2, a few 10 6 strips Events tagged every bunch (300ns) during the overall train (1 ms) Data taking/pre-processing ~ 200 ms Occupancy: < a few % Goals: Low noise preamplifiers Shaping time (from 0.5 to 5 µs, depending the strip length) Analogue sampling Highly shared ADC sparsification Very low power dissipation Power cycling Compact and transparent First LPNHE prototype fulfills most of these goals NEW!! SiLC

Eunil Won/Korea U33 Two designs SCIPP-UCSC: Double-comparator discrimination system  Improve spatial resolution (25%) Next foundry: May 9. LPNHE-Paris: Analogue sampling+A/D, including sparsification on sums of 3 adjacent strips. Deep sub micron CMOS techno. First chip successfully submitted and now under test Next version: in progress SiLC

Eunil Won/Korea U34 LPNHE chip: layout results & tests 3 mm 1.6 mm Shaper: simu vs measurement the layout: ch.(Nov 04)the chip (Feb 05) the test board VERY ENCOURAGING FIRST RESULTS SiLC

Eunil Won/Korea U35 DSSD’s from Latest Fab out P-side IV CV P-side Guard Ring ~ All P-strips ~ No extremely Leaky P-strips Full Depletion Voltage ~100V Operation Voltage ~120V DSSD by J. Lee

Eunil Won/Korea U36 S/N of DSSD 32ch pattern (bulk signal) Signal mean = Pedestal mean = Pedestal sigma = 15.9 S/N = 24.9 Readout system (pad) with VA1 being prepared DSSD

Eunil Won/Korea U37 Vertex/Tracking Summary R&D status of FPCCD vertex detector - Doublet option studied - Lorentz angle : 12 3T GEM TPC beam test result Micromegas TPC beam test result Silicon tracking for ILC (for SiLC) - first prototype on various length Si detectors - readout R&D ongoing DSSD R&D Status - latest fab. result promising - hybrid readout in progress both results are very promising