CADENCE CONFIDENTIAL 1CADENCE DESIGN SYSTEMS, INC. Cadence Formal Verification 2003 Beijing International Microelectronics Symposium C. Michael Chang Vice President, Formal Verification

CADENCE CONFIDENTIAL2 Cadence Formal Overview Formal verification market leader Complete formal verification solution Proven technology s of design tapeouts Comprehensive ASIC vendor & foundry support >300 customers worldwide Firmware IR Drops Power Mixed Signal Intf Yield Race Condition Slow Path Clocking Noise Functional 0%10%20%30%40%50%60%70%80% 100% 74% 33% 31% 24% 23% 21% 14% 11% 10% October 2000 Collett International Half of all chips today require 1 or more re-spins 74% of all re-spins are due to functional errors Source: Dataquest, * EDAC Avant! + Synopsys

CADENCE CONFIDENTIAL3 Ensures consistency of two designs Exhaustive verification using mathematical algorithms Orders of magnitude faster than simulation No test vectors required Pinpoints errors quickly Simplifies analysis and debug of implementation errors Equivalence Checking (EC) Introduction Gate: Post Synth, P&R Etc. RTL or Gate Implementation Verification Conformal EC

CADENCE CONFIDENTIAL4 Conformal Solution Comprehensive Equivalence Checking Solution Memory Datapath Memory Random Logic Random Logic Custom logic, I/O cells EC for Random Logic Verifies synthesized logic EC for Embedded Memory Verifies custom memories EC for Complex Datapath Verifies compiled datapath EC for Digital Custom Verifies custom logic, IO cells, libraries Semantic & Structural Checks Verifies buses and synthesis pragmas EC for Layout Verifies physical integration Clock Domain Crossing Checks Verifies clock synchronization

CADENCE CONFIDENTIAL5 Used throughout the implementation process Independently developed technology Production proven on 1000s of designs Best performance “Conformal by far blows away Formality in speed and capacity.” - Bob Lawrence, Agere Systems Conformal Equivalence CheckerRTL Logic Optimization Floor Planning Placement Logic Synthesis Test Insertion Routing P&R Optimization ECOs Clock Synthesis Conformal ensures implementation equivalence Conformal Solution Implementation Verification

CADENCE CONFIDENTIAL6 Conformal Solution Extends EC to Complex Datapath Trends indicate increased usage of advanced datapath optimization Used to create high performance and area optimized circuits Conformal provides formal verification solution for complex datapath Exhaustive verification Magnitudes faster than simulation Easier to pin-point errors and debug Conformal EC Datapath Synthesis Gate RTL Equivalence Checked " Verifying datapath circuits has been very difficult and time consuming in the past, but we have found Conformal DP to be very efficient in comparing different types of datapath circuits." Hiroshi Furukawa, System-on-a-Chip Design Division of NEC Micro Systems

CADENCE CONFIDENTIAL7 Operator Merging ABC Y X + A B C Y Merged Operator Advanced Pipeline Support Conformal Solution Complex Datapath Support Handles advanced datapath optimization techniques including operator merging and advanced pipelining Flexible – Flattened or hierarchical Supports wide variety of datapath architectures from many datapath synthesis vendors First EC tool to successfully verify complex datapath circuits

CADENCE CONFIDENTIAL8 Conformal Solution Closing the RTL to GDS Verification Gap Final Circuit Final GDS RTL Model Gate Model LVSEC Physical Design Layout integration Circuit optimization Netlist Conversion GDS edits Physical design process can introduce logic errors creating a risk of silicon failure LVS doesn’t check logic errors

CADENCE CONFIDENTIAL9 RTL Model Gate Model EC Final Circuit Final GDS LVS Physical Design Layout integration Circuit optimization Netlist Conversion GDS edits Equivalence Checker Circuit Abstraction Conformal EC Conformal Solution Closing the RTL to GDS Verification Gap Conformal ensures RTL to GDS equivalency

CADENCE CONFIDENTIAL10 Traditional verification method (spice) inadequate for large circuits Conformal provides exhaustive verification capabilities Magnitudes faster than simulation Supports IO cells, custom datapath, and standard cell libraries Conformal Solution Extends EC to Digital Custom Circuits Equivalence Checked RTLCircuit Conformal EC

CADENCE CONFIDENTIAL11 Targets customer designed embedded memories Exhaustive verification without vectors Verifies complex control, scan, BIST, etc… Magnitudes faster than simulation Supports RAM (single & multi-port), CAM (binary & ternary), and register files Equivalence Checker Conformal EC Solution Circuit Abstraction Equivalence Checked RTL Spice Netlist RTL With MEM Primitive Memory Primitives Cadence Memory Primitive Conformal Solution Extends EC to Memories

CADENCE CONFIDENTIAL12 Conformal Solution Providing a Safer EC Environment Complements EC flow Automatic extraction and verification: –Clock Domain Crossing (CDC): Clock synchronization & data transfer validation –Semantics: Verification of synthesis pragmas & assumptions –Structural: Implementation checks including bus & tri-state Can validate checks that don’t exist in RTL Finds difficult implementation bugs

CADENCE CONFIDENTIAL13 CLK A CLK B  Divergent synchronizers Graycode violations Data stability violations Potential CDC glitches Metastability problems Conformal detects Clock topology problems Pinpoint problems quickly Automatic detection of clock domains and crossings Structural verification of multiple clock domain synchronization Functional verification for data stability violations Automates error-prone manual post static timing analysis process Reduces risk of clock related re-spins Prevents late clock related iterations in the design cycle Conformal Solution Clock Domain Checking

CADENCE CONFIDENTIAL14 RTL (a or b or s) begin case (s[1:0]) //synthesis full_case 2’b01: q = a; 2’b10: q = b; endcase end (a or b or s) begin case (s[1:0]) //synthesis full_case 2’b01: q = a; 2’b10: q = b; endcase end Gate-levela s[1] q b Simulation s[0] q RTL: q s[1] Gate: q a a 10 Synthesis 0 1 b b 1 0 a a 1 b a 1 Conformal Solution Semantic Checks Conditions that may create mismatches between RTL and gate-level simulations Full case Parallel case X-assignment Range Overflow Conformal checks if unexpected conditions can exist in design: s[1:0] == {0,0}, s[1,0] == {1,1} Finds functional mismatches that are otherwise missed or detected only by gate level simulation late in design cycle Equivalency can not find this type of error EC follows synthesis interpretation Conformal finds semantic corner-case bugs earlier

CADENCE CONFIDENTIAL15 Conformal Solution Structural Checks Class of bugs typically found late in design cycle, if at all May not be present in “RTL”, scan insertion errors Introduced during design integration Introduced during implementation and ECOs Bus Checks Bus contention Bus or net driven by conflicting data Bus floating Bus is not driven by any signal Tri-state Stuck-at problem with tri-state driver enable Set / Reset Check Set and Reset on at the same time Multi-port Latch Check Multi-port latches loaded with conflicting values Bus errors are a common source of silicon failure Sequential analysis for bus contention 0 q Conformal finds all structural consistency problems both during design and implementation cycles

CADENCE CONFIDENTIAL16 Conclusion The verification problem continues to grow at an exponential rate Simulation-based techniques cannot meet the challenge alone Formal analysis is a critical requirement for thorough verification Equivalence checking is used throughout the implementation process Conformal offers the only comprehensive EC solution for complex SoCs Conformal technology was developed independently to maintain verification integrity