1 An FPGA-Based Novel Digital PWM Control Scheme for BLDC Motor Drives 學生 : 林哲偉 學號 :M9920110 指導教授 : 龔應時 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL.

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1 An FPGA-Based Novel Digital PWM Control Scheme for BLDC Motor Drives 學生 : 林哲偉 學號 :M 指導教授 : 龔應時 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009

2 Outline Abstract INTRODUCTION BRUSHLESS DC MOTOR DRIVE STRATEGIES DIGITAL PWM CONTROL OF BLDC DRIVES CONTROLLER DESIGN DESCRIPTION OF EXPERIMENTAL SETUP SIMULATION RESULTS AND EXPERIMENTAL VERIFICATION CONCLUSION

3 Abstract Development of advanced motor drives has yielded increases in efficiency and reliability. Residential and commercial appliances such as refrigerators and air conditioning systems use conventional motor drive technology. The machines found in these applications are characterized by low efficiency and high maintenance.

4 In a market driven by profit margins, the appliance industry is reluctant to replace the conventional motor drives with the advanced motor drives (BLDC) due to their higher cost. A simple novel digital pulse width modulation (PWM) control has been implemented for a trapezoidal BLDC motor drive system. The novel controller is modeled and verified using simulations. Experimental verification is carried out using field- programmable gate arrays to validate the claims presented.

5 INTRODUCTION An ELECTRIC motor is defined as a transducer that converts electrical energy into mechanical energy. In the case of dc machines, they require more maintenance due to the presence of brushes. Replacing these inefficient motors with more efficient brushless dc (BLDC) motors will result in substantial energy savings.

6 In this paper, a novel digital PWM controller has been proposed for a BLDC motor. This controller treats the BLDC motor as a digital system. The BLDC system is only allowed to operate at a low duty (DL) or a high duty (DH). In addition, this technique utilizes only one current sensor in the dc link. This helps reduce the cost and complexity of motor control hardware. Computer simulations and experimental results are presented for proof of concept.

7 BRUSHLESS DC MOTOR DRIVE STRATEGIES The typical inverter drive system for a BLDC motor is shown in Fig. 1. Fig. 1. Typical inverter drive system for a BLDC motor.

8 In order to get constant output power and, consequently, constant output torque, current is driven through a motor winding during the flat portion of the back-EMF waveform. shown in Fig. 2. Fig. 2. Back EMF and phase current variation with rotor electrical angle.

9 It is important to know the rotor position in order to follow the proper energizing sequence. A timing diagram showing the relationship between the sensor outputs and the required motor drive voltages is shown in Fig. 3. Fig. 3. Sensor versus drive timing.

10 The input sensor state and the corresponding drive state required for commutation can be put in the form of a state table as shown in Table I.

11 DIGITAL PWM CONTROL OF BLDC DRIVES The general structure of a current controller for a BLDC motor is shown in Fig. 5. Fig. 5. Conventional PWM current control.

12 This paper presents the design, simulation, and experimental verification of a novel constant-frequency digital PWM controller which has been designed for a BLDC motor drive system. shown in Fig. 6. Fig. 6. Flowchart describing the novel digital control.

13 This paper presents a controller with no need of any state observer. Fig. 7 shows the proposed digital controller. Fig. 8 shows the complete block diagram of the motor drive system. Fig. 8. Block diagram for digital PWM control for a BLDC motor drive system. Fig. 7. Proposed digital control.

14 A proportional controller provides the reference for the current limit. The minimum value of Ilimit decides the steady-state error. The proportional constant K for a desired speed ripple can be calculated as follows. In steady state, Δω ≤ |ωerr ∗ 2|. In the worst case, Δω = |ωerr ∗ 2|. For the desired speed ripple Δω, a constant Kset can be defined as

15 Taking the maximum value of the speed ripple As long as In addition, Ilimit α ωerror By using (1)–(3) in (4), it can be shown that

16 In this control strategy, both the high- and low-side switches are switched simultaneously. Both high- and low-side diodes conduct. The waveforms for this type of switching are shown in Fig. 9. Fig. 9. Gate switching waveforms.

17 CONTROLLER DESIGN The value of D can be expressed as a function of the motor parameters. From the torque equation, we have

18 DESCRIPTION OF EXPERIMENTAL SETUP The experimental setup is shown in Fig. 12. Fig. 12. Final experimental setup.

19 TABLE II DATA SHEET FOR BLDC MOTOR FROM POLY-SCIENTIFIC

20 The actual speed was easily calculated as a time between two Hall effect signals. The schematic of the controller simulated in the FPGA is shown in Fig. 13. Fig. 13. Block diagram showing operations and functions implemented in FPGA device.

21 SIMULATION RESULTS AND EXPERIMENTAL VERIFICATION For the verification of the control scheme, several operating conditions were selected. Fig. 14. Simulated duty, speed, and current response for a commanded speed of 2500 r/min for full-load operation.

22 Fig. 15. Experimental results for a reference speed of 2500 r/min under no load condition. Fig. 16. Experimental results for a reference speed of 2500 r/min. Load is 30% of rated value.

23 Fig. 17. Experimental results for a reference speed of 1500 r/min under no load condition. Fig. 18. Experimental results for a reference speed of 1500 r/min. Load is 30% of rated value.

24 Fig. 19. Experimental results for a reference speed of 2100 r/min under full load.

25 Fig. 20. Speed response for change in load torque and for a reference speed of 2000 r/min. Fig. 21. Experimental results for a change in reference speed from 2200 to 1300 r/min under no-load condition.

26

27 CONCLUSION The aim of this paper is to develop a low-cost controller for applications where inefficient single-phase induction motors are used. Due to the simplistic nature of this control, it has the potential to be implemented in a low-cost application-specific integrated circuit. Furthermore, this control strategy does not require a state observer. Under dynamic load conditions, the proposed controller was found to be capable of regulating speed without the use of an observer. This results in a considerable reduction of size and the cost of the system.