LLRF FOR THE SPS 800 MHZ CAVITIES G. Hagmann, P. Baudrenghien 12/12/2013LIU meeting 1

Block diagram 12/12/2013LIU meeting 2

800 MHz TX-cavity chain Cavity: 12/12/2013LIU meeting 3 Centre freq MHz Phase advance per cell  /2 Group velocity v g /c Cell length93.5 mm Total length L (37 cells)3.460 m Series impedance R M  /m  MHz

800 MHz TX-cavity chain (cont’d) TX (IOT) :  1  3 MHz -4  5 MHz 12/12/2013LIU meeting 4 Measurement reproduced from Eric’s presentation Conclusion: We aim at minimum ±6 MHz Closed-Loop bandwidth

Vector sum 12/12/2013LIU meeting 5

New 800 MHz System (VME) LL Cavity 1LL Cavity 2 12/12/2013LIU meeting 6 LL Cavity 1LL Cavity 2 LL Common

New 800 MHz System (VME) RFFGCMMSwitch&Limit Cavity Loops 200MHZ Quadrupler Clock Distributor Linux FrontEnd CTRV VME bus (A24D16) RF LowLevel Backplane 12/12/2013LIU meeting 7

VME Cards Switch & Limit Clock Distributor RF design & FPGA (Controls, Acquisitions,…) on the same board 12/12/2013LIU meeting 8 J.Lollierou, J.Noirejan, G.Hagmann G.Hagmann

VME Cards 200MHZ Quadrupler 12/12/2013LIU meeting 9 RF Function generator M.Naon, T.Levens, G.Hagmann G.Hagmann

12/12/2013LIU meeting 10 3rd HiLumi LHC-LARP SSB Modulator IF (I & Q) ≈25MHz Dual TxDac 16 bits RF Demodulator RF&LO mixing IF ≈25MHz 14 bits ADC Fs=4·IF ≈100MHz 4x LO Distribution 2 x Duplex Optical Serial Links 2 in & 2 out 2Gbits/s (≤3.2Gbits/s) SRAM 2x8 Mbyte for diagnostics VME P1 backplane for slow controls/read out Dedicated backplane (P2): Power Supply Clocks Interlocks … Xilinx Virtex-5 SXT G. Hagmann BE-RF-FB designer Cavity Loops v1

Module NameStatus Status Software Linux Front-end (CPU) Installed NR CTRV (timing)Installed OK CMM (Crate Management) Installed OK WBS (Wide Band Switch) LHC Spares available - RFFG (Function generator) under designInstalledOK Switch&LimitProto V2 under testV3 pre-series in prod.From L4 Clock DistributorProto V2 under testProto V3 under testFrom L4 200MHz QuadruplerProto V1 in prod.V2 in prod.NR Cavity Loops (RF Feedback) Under designV1 availableFrom L4 Veto SumUnder specification - Antenna Vector Sumunder designProto “Vector mod.” under testNR Status 12/12/2013LIU meeting 11

Cavity Loop : IQ demodulation TWC 800 MHz Frequencies : LO = 31/8 * Frf 200 ≈ 775 MHz Fs = Frf 200 / 2 ≈ 100 MHz F if = Fs/4 ≈ 25 MHz Fs 12/12/2013LIU meeting 12 Acquisition 14Bits, 100MSPS => ENOB ≈ 11bits (12MHz) => Channels crosstalk < 11bits The 800 MHz RF signals (waveguide coupler or cavity sum) are mixed down to a 25 MHz RF using a 775 MHz LO. The IF is then sampled at 100 MSPS

12/12/2013LIU meeting 13

TWC 200 MHz Phase Σ 12/12/2013LIU meeting 14

Filters (implementation) 12/12/2013LIU meeting 15

Mid-1980s Comb filter 12/12/2013LIU meeting 16 The OTFB must have large gain on the exact revolution frequency sidebands (f RF  k·f rev ) to fully compensate the transient beam loading. The result will be a precise amplitude/phase ratio of MHz RF for all bunches The OTFB must also have gain on the synchrotron sidebands (f RF  k·f rev  m·f s ) to reduce the real part of the effective cavity impedance. The result will be an increased threshold for longitudinal coupled-bunch instability. We aim at covering dipole mode (m=1) with full gain, and some gain for the quadrupole mode (m=2) The synchrotron frequency range is LHC 25ns, Q20 f s < 1 kHz Fixed target, Q26f s < 1.4 kHz LHC ion, 12inj, Q20:f s < 2.2 kHz With the classic simple IIR filter, the maximum gain G is inversely proportional to the bandwidth (around the revolution frequency lines) The required minimum 2 kHz -3 dB BW, results in a maximum gain of 2 linear. Not very impressive! Conclusion: The simple IIR filter cannot be used

A Modern Comb filter 12/12/2013LIU meeting 17 Step1: Decimation by R=5 (?) -> 20 MSPS Step2: FIR structure at 20 MSPS Step3: Interpolating LPF FIFO, N=462 The gain and BW can now be defined independently, at the expense of filter complexity. For example G=17 (25 dB), ±3 kHz BW in the above design (15 taps) 36 dB stopband attenuation 6 kHz 2-sided BW around the frev lines 8 MHz single- sided -3 dB BW

Cavity filter The cavity impedance is real-valued. Its sign flips at multiples of 3.2 MHz frequency We will compensate this with an all-pass filter with zeros at these frequencies This filter will be implemented in the FPGA, after the RF synchronous demodulation, but its response must not follow the ramping RF frequency (almost 2 MHz drift at 800 MHz for FT beams) Freq Fcav MHz ~3.2MHz Frf flat top ~801.6MHz ∆f=+0.71MHz Frf flat botom ~799.8MHz ∆f=-1.12MHz 12/12/2013LIU meeting 18

Cavity filter (in baseband) The Filter is implemented with digital circuitry operated with a beam synchronous clock We compensate this by 1.down modulating the antenna signal by the beat frequency (∆f=Frf – Fcav) 2.filtering with beam synchronous clock 3.Up modulating ∆f F F Before Filtering F ∆f After Filtering 12/12/2013LIU meeting 19 ∆f RF200 ≈ 450 KHz, ∆f RF800 = 4∙∆f RF800 ≈ 1.8MHz = ∆f  57% wrt to 1 st zeros (3.14MHz) !! But the zeros still move (negligible): ~3.14∙0.45/200 ≈ 7kHz (  = 0.23%) A candidate sign-flipping filter

RF ON-OFF Modulation The generation of harmonically related clocks for demodulation (LO) and sampling require a stable, 200 MHz reference locked to the varying revolution frequency during the cycle: Frequency Program output? Modulation of the 800 MHz can be applied at the set-point level The ON-OFF modulation of the 200 MHz will require some additional treatment to extract 200 MHz phase in CavLoop module. Manageable 12/12/2013LIU meeting 20

Operation with Ions (preliminary) We could use the 200 MHz RF-AVG (= 4620 f rev ) as reference for generation of the clocks Compensation of transient beam loading would work correctly with fixed frequency acceleration as it depends on the revolution period only The tracking of the 200 MHz phase must be studied 12/12/2013LIU meeting 21 Sawtooth Frf200 Frf avg (ions)

Planning The two cavities are equipped with antenna on all cells 1 antenna per cell The Antenna Summing network is being designed Help from D. Valuch Prototype beginning of 2014 Electronics pre-series & prototype are available or being produced Tests beginning 2014 We are developing the following firmware functionalities for start-up 1T-delay feedback 200MHz cavity sum phase extraction Polar loop (if time allows) The design will be adapted according to these first results We would benefit from a period with IOT-Cavity but without beam, during SPS hardware commissioning, at start-up 12/12/2013LIU meeting 22

Thank you for your attention… 12/12/2013LIU meeting 23

References [1] D. Boussard et al., Controls of Strong Beam Loading, IEEE Transaction on Nuclear Sciences., 1985 [2] P. Baudrenghien et al., Control of strong beam loading. Results with beam, Chamonix 2001 [3] T. Mastoridis et al., RF system models for the CERN Large Hadron Collider with application to longitudinal dynamics, Phys. Rev. Sp. Topics. AB, 13, , 2010 [4] P. Baudrenghien et al., The LHC RF System. Is it working well enough ? Chamonix 2011 [5] D. Boussard, Travelling-Wave structures, Joint US-Cern-Japan Intl School, Tsukuba, 1996 [6] P. Baudrenghien, CAS RF 2000 and /12/2013LIU meeting 24

Back-Up slides 12/12/2013LIU meeting 25

CavityLoop : Up-modulation RF Modulation, SSB 16Bits DACs: 12/12/2013LIU meeting 26 Low phase noise: (LO from Agilent E8663B still) Span : 20MHz SFDR > 100dB ∆  : +/- 1° ∆G : +/- 0.5dB phase Gain