File Number Here CPLD Competition

File Number Here Session Objectives  Review Strengths & Weaknesses of key competitors: —Lattice —Vantis —Altera  Highlights areas to attack and win

File Number Here Competitor Profile: Vantis (AMD)  Old AMD PLD division —now a separate fabless company —dependent on AMD fabs (+ UMC for FPGA in ‘98) —SPLDs and CPLDs now; announced new ‘VF1’ FPGA line  Minimal software, customer service functions —management focused only on components, not solutions —relies on AMD for process development  Dropped down to 4rd largest PLD company —fell from 3rd in ‘97 behind Lattice —dependent on declining SPLD sales

File Number Here Vantis Thrust Products  Mach 4LV: 3.3V Low & Mid density ISP —32 to 256 macrocells —speeds to 7.5ns (slower than 5V devices) —good JTAG support  Mach 5LV: 3.3V High-density ISP —128 to 512 macrocells —raw speeds to 7.5ns, but only specific input-output paths —good JTAG support  Other products —5V versions of Mach4, Mach5 —Mach 1,2,3: Low density, some with ISP retrofit

File Number Here Vantis Weaknesses (Present)  Clumsy Software —clumsy software developed by 3rd party (MINC) —re-starting in-house SW group (little effect in short term) —poor support for Mach5/LV  High prices due to high cost structure —“0.35um” process has 0.5um feature size  Mach5/LV difficult to achieve speed/utilization —path-dependent delays —block-localized features cause routing difficulties –power reduction, output enables

File Number Here Vantis Weaknesses (Future)  Concern over future plans —will business be sold (and obsoleted)? —reference: Intel PLDs sold to Altera and obsoleted  Reduced CPLD focus —resources consumed by FPGA launch —slow cost migration, product improvements, software improvements

File Number Here Vantis Attack Points  Attack the software —what is the software roadmap ?  Attack device volume availability —enough priority/capacity from AMD fabs?  Attack Mach5/LV architectural limitations —block-localized power reduction, OEs restricts fitting and routability —complex 3-tier routing structure, path-dependent timing  Attack technical support —call Vantis, Minc, or ? for routing issues

File Number Here Competitor Profile: Lattice  1st with ISP CPLD, but an incomplete solution —pin-locking issues —old fashioned architecture —Non-standard ISP interface (proprietary non-JTAG)  Biggest supplier of ISP CPLDs —several different but similar CPLD families —1997 CPLD market share is about 20%  Reputation for inadequate software solution

File Number Here Lattice Thrust Products  ispLSI2000V: —3.3v ISP (de-rated 5V parts) —2032V offers no power savings over same speed 5V 2032 —latch-up risk in mixed 3.3V/5V systems —higher cost, slower speed grades than 5V versions  ispLSI1000E/2000 —32 to 192 macrocells —improved routing, but not enough  Other products: —ispLSI3000: large & difficult-to-use (192 to 320 macrocells) —ispLSI6000: 192 macrocells Kbit RAM

File Number Here Lattice Weaknesses (Present)  Software performance —hampered by the restrictive silicon architecture —ease of use issues —pin-locking issues —poor routing at high utilization  Restrictive, 6-year old architecture —limited product-term allocation options —no individual output enables (OE) —block-localized clock signals

File Number Here Lattice Weaknesses (Future)  Proprietary, non-standard ISP interface (ispLSI1K/2K) —difficult board integration with JTAG components  Limited to CPLD devices only —against industry trend toward a single logic vendor

File Number Here Lattice Attack Points  Attack 3.3V IC deficiencies: —latch-up risk (requires significant design effort to compensate) —no or minimal power savings over 5V —slower, higher price  Attack software capability —why can’t use more than 80% device utilization?  Attack EEPROM process roadmap —what is the long-term process migration path?  Lack of JTAG on lead products (ispLSI 1K/2K)

File Number Here Competitor Profile: Altera  Largest supplier of CPLDs —note: Flex 8K and 10K are not CPLDs  Company focused on IC/software technology —not focused on solutions or customer support

File Number Here Altera Thrust Products  Max7000A —3.3V ISP —no enhancements over 7000S, only fixes  Max7000S —old Max7000(E), but with ISP —32 to 256 macrocells  Flex10K —really an FPGA, not “CPLD”  Other products: —Max9000: 300 to 560 macrocells, with ISP —Flex 8K: FPGAs called “CPLDs”

File Number Here Altera Weaknesses (Present)  Pin-locking is well-known issue —especially > 100 macrocells —EEPROM-based sparse routing matrix —“2nd time fitting” is not pin-locking –Altera measures software ability to refit the same design to locked pins –veteran Max7K users burnt by pin-locking problem  7-year-old basic architecture —less flexible vs. XC9500 in product-term allocation —no individual (p-term) output enables —only 2 global clocks

File Number Here Altera Weaknesses (Future)  Proprietary EEPROM technology pushed to its limits? —persistent problems with new TSMC fab after 3+ years —slow and problem-prone roll-out of Max7000S  Market trend is for standard design language —move to VHDL erodes AHDL design wins  Architecture problems hidden by software —auto-picks bigger devices to reduce % utilization —error messages say “No” very nicely

File Number Here Altera Attack Points  Attack AHDL fortress —no design portability —convert AHDL designs to VHDL —sell Foundation with VHDL upgrade  Attack reliance on old architectures and processes —XC9500 is new technology, new benefits  Attack ISP device availability, quality —sampled defective devices to customers with charge loss problems —3 year delay on Max7000S family rollout —only 100 program/erase cycles, 10 year data retention

File Number Here Reference Materials

File Number Here Pin-Locking Comparisons Xilinx XC9500 Altera Max7KS Lattice 1K/2K/3K AMD Mach5 Routability Function block fan-in Bi-directional individual product term allocation Maximum pterms/MCell Excellent 36 Yes 90 Good* 36 No 32 Poor 18/24 No 20 Good 32 No 32 Notes: * Increasingly worse with density

File Number Here JTAG Comparison XC9500 Benefits USERCODE INTEST IDCODE HIGHZ Version control JTAG Instruction Capability Altera Max7KS Xilinx XC9500 Yes No Yes No Lattice isp AMD Mach5 No Yes Yes* Not in 1K/2K Yes Extest Sample/Preload Bypass Basic boundary scan Notes: * JTAG boundary-scan is NOT available in the 7032S, 7064S, and 7096S. In-system debug Device type ID Tristate pins during test 4 Built-in version control for pattern tracking 4 Efficient system debugging / diagnosis

File Number Here XC9500 = Most Flexible Architecture Altera Max7KS Lattice 1K/2K/3K AMD Mach5 Individual set, reset, clock pterms Individual OE pterm for each pin 3.3v/5v I/O Number of global clocks True / complement global clocks Global set/reset User programmable grounds Maximum # pterms per macrocell Yes 3 Yes 90 Yes No Yes 2 Yes Reset No 32 No 3 1K Only Reset No 20 No Yes 4 Yes No 32 4 Superior pin-locking architecture 4 Enhanced logic capability 4 Efficient logic implementation Leading-Edge Architecture Benefits Xilinx XC9500 Notes: * 7032S is the exception and does NOT provide 3.3v/5v I/O capability.

File Number Here Product Comparison Altera Max7KS Lattice 1K/2K/3K AMD Mach5 Description Macrocell range Number of user I/O pins Best tPD Best fMAX 5V in-system programmable Pin-locking Endurance (pgm/erase cycles) JTAG boundary-scan Number of JTAG instructions 3.3V ISP versions ns 125MHz Yes Good 10,000 Yes 7 2H ns 179MHz Yes Fair-Poor only 4* 2Q ns 180MHz Yes Poor 10,000 3K only V ns 125MHz Yes Fair 100 Yes 6 MachLV Notes: * JTAG boundary-scan (1149.1) is NOT available in the Altera 7032S, 7064S, and 7096S. Xilinx 9500