TRBnet for the CBM MVD-Prototype Borislav Milanović In cooperation with: J. Michel, M. Deveaux, S. Seddiki, M. Traxler, S. Youcef, C. Schrader, I. Fröhlich, C. Müntz

Overview 1/22 Overview

2/22

HADES Specifications data channels 520 PCBs / 550 FPGAs 6 Detector Systems Au Au:  20 kHz trigger rate (10 5 collision rate)  200 particles/event  200 MByte/s – Specifications 3/22

Protocol  HADES and FAIR  DAQ  FPGA + Optical Links Network  Unified Bus  Secure Transmission TRBnet ? – Explanation 4/22

372 x 30 x 6 x 9 x 24 x 4 x 12 x 3 x 2 x 20  2 GBit/s – Network 5/22 - Jan Michel, „Status of the HADES Upgrade“ -

6/22 TRBnet Key Features

Architecture Optical Network Detector 2 Detector n Trigger System Data Processing Slow Control Detector 1... TRBnet Key Features – Architecture 7/22

Dataflow Optical Network Detector 2 Detector n Trigger System Data Processing Slow Control Detector 1... TRBnet Key Features – Dataflow 8/22 Max. 3 μs latency

TRBnet Specifications Layers Unique IDs CRC checksum addr1addr2addr3 CRC 5 x 16bit Four prioritized virtual Channels TRBnet Key Features – Specifications 9/22

TRBnet Specifications Channel 1 Trigger Data Channel 2 Event Data Channel 3 Slow Control Channel 4 Monitoring 1 Optical Link TRBnet Key Features – Channels Channel switching after each data packet 10/22

TRBnet Facts 80 bit/packet, 64 bit payload  Overhead 16 bit! Error detection  No inconsistent data through transport Secure Transfers  All boards answer each transfer Independent on underlying System/Data TRBnet reduces net-bandwidth to 63%  E.g. Optical Link 3 Gbit/s 2 Gbit/s TRBnet Key Features – Facts 11/22

12/22 MVD Requirements

MVD MVD Requirements – Geometry MAPS 13/22

Station 1 Simulation MVD Requirements – Station 1 simulation 14/22 Data Rate per Sensor [MByte/s] - Sélim Seddiki, „MVD DAQ Prototype“ - 1 prototype Au 25GeV 5  10 5 collision rate T int = 10 μs approx. 7 GByte/s

MVD Prototype MimoSIS-1 M26 high-res. inspired 3 cm 2 MVD Module: 2-sided, 0,37 between sensors: 2 x 50 µm Si, 300 µm CVD-Diam., 2 x 35 µm Glue → 350 µm Si equ, (0.37 % X0), Ø 359 µm Si equ, (0.383 % X0) 5 sensors / module 500 µm overlap of opposite sensors (pitch: ~ 20 µm) 9 cm 2 - Christian Müntz -  5  4 = = 15/22 MVD Requirements – Prototype

Comparison Main challenge:  40 Gbit/s  Self-Triggering MVD Requirements – Datarate HADESMVD 20 kHzNonstop MB/s5 GB/s (Prototype) 16/22 Trigger Particles Datarate

17/22 Evaluation and Future Actions

Scheme FPGA TRBnet HUB FPGA... => 25 optical links 2 Gbit/s effective*... Evaluation and Future Actions – Readout 40 Gbit/s *Bandwidth depends on the FPGA frequency TRBnetMVD-Prototype 18/22

Scheme 19/22 Evaluation and Future Actions – Readout FPGA TRBnet HUB FPGA TRBnet... 2 Gbit/s effective* *Bandwidth depends on the FPGA frequency => 25 optical links 40 Gbit/s MVD-Prototype 8b10b + twisted pair copper ROC

First Steps MAPS Addon Board with PEXOR Card  First TRBnet implementation for MAPS TRBnet Hubs  Datarate simulation 1 MAPS PC 20/22 Evaluation and Future Actions – First steps data

Summary TRBnet is ideally suited for the first MVD prototype simulations ▫Already implemented ▫Highly modular (written in VHDL) ▫Various configurations ▫Low latency (3 μs), decent bandwidth (63 %) ▫Extensible - new designs, larger data buffers Tested on XILINX and Lattice HADES ▫up to 100 MHz, 16bit data format First steps towards the ROC 21/22 Evaluation and Future Actions – Summary

References J. Michel, „Development of a Realtime Network Protocol for HADES and FAIR Experiments“ J. Michel, „Status of the HADES Upgrade“ I. Fröhlich, „The Readout of the CBM MVD“ M. Deveaux, „Status of the Micro Vertex Detector of the CBM Experiment“ S. Seddiki, „MVD DAQ Prototype“ 22/22 References