Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 71 ELEC 5270/6270 Spring 2015 Low-Power Design of Electronic Circuits Energy Source Design Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Outline Energy source optimization methods Energy source optimization methods Voltage and Clock Management Voltage and Clock Management Functional Management Functional Management Voltage and Clock Management (DVFS) Voltage and Clock Management (DVFS) Background Background A typical system powered with battery A typical system powered with battery Battery Simulation Model Battery Simulation Model DC to DC converter DC to DC converter Problem statement Problem statement Case I : System is Performance bound Case I : System is Performance bound Case II : A higher battery lifetime is required Case II : A higher battery lifetime is required Case III : Battery weight or size is constrained Case III : Battery weight or size is constrained Copyright Agrawal, 20112ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Timing Management Functional Management Voltage Management Energy Source Optimization Methods Dynamic Voltage Management Multi-Voltage design Dynamic Frequency Management Retiming Fetch Throttling Dynamic Task Scheduling Instruction Slowdown Low Power solutions to common operations e.g. Low Power FSMs, Bus Encoding etc Dynamic Voltage and Frequency Scaling (DVFS) ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Timing Management Functional Management Voltage Management Energy Source Optimization Methods Dynamic Voltage and Frequency Scaling (DVFS) Instruction Slowdown Method in Processors Parallel Architectures ELEC5270/6270 Spr 15, Lecture 7

Powering a System Copyright Agrawal, VBVB +_+_ RBRB VLVL RLRL ILIL AHr (capacity) ELEC5270/6270 Spr 15, Lecture 7

Current and Load Power Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 76 Current: I L = V B / (R B + R L ) Power supplied to load: P L = I L 2 R L = V B 2 R L / (R B + R L ) 2 P Lmax = V B 2 / (4R B ), maximum power when R L = R B

Battery Lifetime, Power, Efficiency Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 77 Power supplied from battery: P B = I L 2 (R B + R L ) = V B 2 / (R B + R L ) Battery Efficiency = P L /P B = R L / (R B + R L ) Ideal lifetime of battery = Ahr / I L = Ahr. (R B + R L ) / V B Where AHr is battery capacity in ampere-hours

Lifetime, Power and Efficiency Copyright Agrawal, Efficiency or Power R L /R B Lifetime (x AHr.R B / V B ) Lifetime Efficiency P L = V B 2 /(4R B ) ELEC5270/6270 Spr 15, Lecture 7 (Maximum power transfer theorem)

Copyright Agrawal, Power Subsystem of an Electronic System DC – DC Voltage Converter Electronic System 4.2 V to 3.5 V Lithium- ion Battery Decoupling Capacitor VDD GND ELEC5270/6270 Spr 15, Lecture 7 See Lecture 12 on Power and Ground from ELEC 7770:

Some Characteristics Lithium-ion battery Open circuit voltage: 4.2V, unit cell 400mAHr, for efficiency ≥ 85%, current ≤ 1.2A Discharged battery voltage ≤ 3.0V DC-to-DC converter Supplies VDD to circuit, VDD ≤ 1V for nanometer technologies. VDD control for energy management. Decoupling capacitor(s) provide smoothing of time varying current of the circuit. Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Battery Simulation Model Lithium-ion battery, unit cell capacity: N = 1 (400mAHr) Battery sizes, N = 2 (800mAHr), N = 3 (1.2AHr), etc. Ref: M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504–511, June ELEC5270/6270 Spr 15, Lecture 7

Model: Battery Lifetime Part SOC: State of charge = V SOC SOC: State of charge = V SOC V SOC = 1 volt, for fully charged battery. V SOC = 1 volt, for fully charged battery. C Capacity = 3600 ✕ AHr-rating ✕ f(Cycles) ✕ f(Temp) C Capacity = 3600 ✕ AHr-rating ✕ f(Cycles) ✕ f(Temp) f(Cycles), f(Temp): effects of dropping capacity with number of recharges and temperature. Both are close to 1. f(Cycles), f(Temp): effects of dropping capacity with number of recharges and temperature. Both are close to 1. R self-Dscharge : A large leakage resistance. R self-Dscharge : A large leakage resistance. Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 712

Voltage-Current Characteristic Determined from experimental data. Determined from experimental data. Open circuit voltage: Open circuit voltage: V = −1.031e −35×SOC × SOC − × SOC × SOC 3 R Series = e – 24.37×SOC R Series = e – 24.37×SOC Other resistance and capacitance are also non-linear functions of SOC and represent short-term (S) and long-term (L) transient effects. Other resistance and capacitance are also non-linear functions of SOC and represent short-term (S) and long-term (L) transient effects. Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 713

Copyright Agrawal, Lifetime from Battery Simulation 1008 sec ELEC5270/6270 Spr 15, Lecture 7

Battery Efficiency Consider: 1.2AHr battery I Batt = 3.6A Ideal Lifetime = 1.2AHr/3.6A = 1/3 hour (1200s) Actual lifetime from simulation = 1008s Efficiency= (Actual lifetime)/(Ideal lifetime) =1008/1200 =0.84 or 84% Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

DC-to-DC Buck (Step-Down) Converter Components: Switch (FETs, VDMOS), diode, inductor, capacitor. Switch control: pulse width modulated (PWM) signal. V s = D · V g, D is duty cycle of PWM control signal. Copyright Agrawal, Source: R. W. Erickson, “DC to DC Power Converters, “ Wiley Encyclopedia of Electrical and Electronics Engineering s ELEC5270/6270 Spr 15, Lecture 7

Asynchronous DC-to-DC Buck Converter Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 717 V ref + – L CLoad VgVg V

An Electronic System Example A 32-bit Ripple Carry Adder (RCA) 352 NAND gates (2 or 3 inputs) 1,472 transistors In order to realize a practical circuit and to generate sufficient current for the battery model, 200,000 copies of RCA were used. That makes it 352 x 200,000 ≈ 70 million gate circuit. Critical path: 32bit ripple-carry adder. Simulation model: 45nm bulk CMOS, predictive technology model (PTM), Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

32-bit Ripple Carry Adder Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 719 A0 B0 C0=0 C1 S0 A1 B1 C2 S1 A31 B31 C32 S31

Critical Path Vectors Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 720 Vector 1 C = A = B = S = Vector 2 C = A = B = S = bits

HSPICE Simulation of 32-Bit RCA, VDD = 0.9V Copyright Agrawal, Average total current, I circuit = 74.32μA, Leakage current = 1.108μA 100 random vectors including critical path vectors ELEC5270/6270 Spr 15, Lecture 7 Critical path vectors 2ns

HSPICE Simulation of 32-Bit RCA, VDD = 0.3V Copyright Agrawal, Average total current, I circuit = μA, Leakage current = 0.092μA 100 random vectors including critical path vectors ELEC5270/6270 Spr 15, Lecture 7 Critical path vectors 200ns

Finding Battery Current, I Batt Assume 32-bit ripple carry adder (RCA) with about 350 gates represents circuit activity for the entire system. Total current for 70 million gate circuit, I circuit = (average current for RCA) x 200,000 DC-to-DC converter translates VDD to 4.2V battery voltage; assuming 100% conversion efficiency, I Batt = I circuit x VDD/4.2 Example: HSPICE simulation of RCA: 100 random vectors VDD = 0.9V, vector period = 2ns, Average current for RCA = 74.32μA, I Batt = 3.18A Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

Case I: Performance Battery should be capable of supplying power (current) for required system performance. Battery should meet the lifetime (time between replacement or recharge) requirement. Power management to extend the lifetime of selected battery. Copyright Agrawal, System is Performance Bound ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Step 1: Determine the lower bound on the operating voltage based on required performance. Step 2: Determine minimum battery size for efficiency ≥ 85% Step 3: Increase battery size over the minimum size to meet lifetime requirement. Step 4: Determine a lower performance mode with maximum lifetime for a given battery. Four Step Design ELEC5270/6270 Spr 15, Lecture 7

Step 1: Find Operating Voltage Consider a performance requirement of 200MHz clock, critical path delay ≤ 5ns. Circuit simulation gives, VDD = 0.6V and I Batt = 477mA. Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Circuit Simulation: Determine Operating Voltage and Current for System Performance 200 MHz 477 mA ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Step 2: Determine Minimum Battery Size For required current 477 mA Battery Efficiency ≥ 85 % Select 400 mAHr Battery ELEC5270/6270 Spr 15, Lecture 7

Simulate Selected Battery A meaningful measure of the work done by the battery is its lifetime in terms of clock cycles. For each VDD in the range of valid operation, i.e., VDD = 0.1V to 1.0V, calculate lifetime using circuit delay and battery efficiency obtained from HSPICE simulation. Minimum energy operation maximizes the lifetime in clock cycles. Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Higher Circuit Speed, Lower Battery Efficiency Higher Battery Lifetime, Lower Circuit Speed DVFS range Simulation of 400mAHr Battery Over entire operating voltage range of 0.1 V to 1 V For both Ideal and Simulated battery (MHz) ELEC5270/6270 Spr 15, Lecture 7

Step 3: Battery Lifetime Requirement Suppose battery lifetime for the system is to be at least 3 hours. For smallest battery, size N = 1 (400mAHr) I Batt = 477mA, Efficiency ≈ 98%, Lifetime = 0.98 x 0.4/0.477 = 0.82 hour For 3 hours lifetime, battery size N = 3/0.82 = 3.65 ≈ 4. We should use a 4 cell (1600mAHr) battery. Copyright Agrawal, System needs higher battery lifetime ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, x10 9 clock cycles, 50 minutes 2540x10 9 clock cycles 205 min ( > 3 Hrs) Meeting Lifetime Requirement (MHz) ELEC5270/6270 Spr 15, Lecture 7

Step 4: Minimum Energy Operation Copyright Agrawal, x10 9 clock cycles 6630x10 9 clock cycles (MHz) ELEC5270/6270 Spr 15, Lecture 7

Summarizing Power Management Battery size VDD = 0.6V, 200MHzVDD = 0.3V, 3.86MHz Effici. % Lifetime Effici. % Lifetime NmAHr x10 3 seconds X10 9 cycles x10 3 seconds X10 9 cycles Copyright Agrawal, > two-times 1.Battery size should match the current need and satisfy the lifetime requirement of the system: (a) Undersize battery has poor efficiency. (b) Oversize battery is bulky and expensive. 2Minimum energy mode can significantly increase battery lifetime. ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, Battery Size or Weight is Constrained 1.Some real life applications call for a fixed size (or weight) of a battery, e.g., bio-implantable devices, hearing aid. 2Performance requirements are secondary and the primary goal is to maximize the lifetime (or number of cycles before next recharge). 3Example: A CR2032(CR) Lithium-ion battery Nominal Voltage: 3V Capacity: 225mAHr Nominal Current: 0.3 mA Maximum Current: 3 mA ELEC5270/6270 Spr 15, Lecture 7

Copyright Agrawal, x10 9 clock cycles (MHz) ELEC5270/6270 Spr 15, Lecture 7

References 1. 1.M. Pedram and Q. Wu, “Design Considerations for Battery-Powered Electronics,” Proc. 36th Design Automation Conference, June 1999, pp. 861– L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “A Discrete-Time Battery Model for High-Level Power Estimation,” Proc. Conference on Design, Automation and Test in Europe, Mar. 2000, pp. 35 – M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504 – 511, June Simulation model: 45nm bulk CMOS, predictive technology model (PTM), Simulator: Synopsys HSPICE, /HSPICE/Documents/hspice ds.pdf /HSPICE/Documents/hspice ds.pdf Copyright Agrawal, ELEC5270/6270 Spr 15, Lecture 7

6. 6.M. Kulkarni and V. D. Agrawal, “Matching Power Source to Electronic System: A Tutorial on Battery Simulation”, Proc. VLSI Design and Test Symposium, July Energy Source Lifetime Optimization for a Digital System through Power Management,” Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System Theory, March M. Kulkarni and V. D. Agrawal, “Energy Source Lifetime Optimization for a Digital System through Power Management,” Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System Theory, March Architectural Power Management for High Leakage Technologies,” Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System Theory, March M. Kulkarni, S. Sheth and V. D. Agrawal, “Architectural Power Management for High Leakage Technologies,” Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System Theory, March Energy Source Lifetime Optimization for a Digital System through Power Management,” Master’s Thesis, ECE Dept., Auburn University, December M. Kulkarni, “Energy Source Lifetime Optimization for a Digital System through Power Management,” Master’s Thesis, ECE Dept., Auburn University, December K. Sheth, “A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management,” Master’s Thesis, ECE Dept., Auburn University, December Copyright Agrawal, References (Cont.) ELEC5270/6270 Spr 15, Lecture 7