CSE Autumn CMOS I - 1 MOS Technology zUnderlying implementation technology of virtually all hardware components in wide-spread use today zObeying Moore's law ydoubling density and performance every 18 months ycertain to continue for the next decade yfundamental limits will be reached soon zUnderstanding of abstract technology provides insight into tradeoffs inherent in hardware design

CSE Autumn CMOS I - 2 "0" "1" openclosed "0" "1" closedopen MOS as an Abstract Technology zTransistors are switches (first-order approximation) zTwo types of transistors are possible n-type: p-type: zAll logic can be built from these simple primitives gate sourcedrain gate sourcedrain

CSE Autumn CMOS I - 3 side view top view diffusion poly metal cuts MOS Technology – Metal/Oxide/Semiconductor zMultiple layers of material on a silicon substrate with intervening insulation zSubstrate is a silicon lattice with doping ions in selected locations zLayers in substrate include n-type and p-type regions zLayers above substrate are polycrystalline silicon, metal (Al, W, or Cu), etc. zInsulating layers is silicon oxide (SiO2 or glass)

CSE Autumn CMOS I - 4 thin oxide between poly and diff form transistor MOS Technology (cont'd) zLayers can be used to electrically connect signals (routing) zLayers above substrate are medium to excellent conductors zLayers in substrate are poor conductors (doped semiconductor) zSubstrate and silicon oxide are excellent insulators zInteraction between polycrystalline silicon (poly) and diffusions creates the transistor that is key to building logic structures

CSE Autumn CMOS I - 5 MOS Transistors zTwo types of diffusion – silicon has 4 electrons in valence shell n-type – doping ions have extra electrons (5 valence, phosphorus) p-type – doping ions have extra holes (3 valence, boron) zPolysilicon over substrate (separated by thin layer of silicon oxide) is used to form channel between two regions of same type of diffusion

CSE Autumn CMOS I - 6 when Vg=Vd=5v, Vs won't go higher than 4v when Vg=Vd=0v, Vs won't go lower than 1v (note: drain and source are symmetric) Realities of MOS Transistors zn-type devices pass "0"s well –– p-type devices pass "1"s well za "1" is 5v and a "0" is 0v in current CMOS technology (moving to 3v) zgate to source voltage (Vgs) must be greater than 1v for n-type device to start conducting (less than -1v for p-type device) gate sourcedrain gate sourcedrain

CSE Autumn CMOS I - 7 ab s d a b s d a b s d ab sd conducts iff ab (0 only) conducts iff a'b' or (a+b)' (1 only) conducts iff a'+b' or (ab)' (1 only) conducts iff a+b (0 only) Switching Logic

CSE Autumn CMOS I - 8 a b 1f(a,b) aba + b Implementation of Logic Gates zOR gate zTwo problems y1) when a=b=0, f(a,b) is undefined (floating) y2) n- type switches do not conduct 1 well zTwo solutions ywhen f=0, connect output to 0v using n-type switches ywhen f=1, connect output to 5v using p-type switches

CSE Autumn CMOS I - 9 inputsoutput P N 5v (logic 1) 0v (logic 0) pull-up pull-down a a' aa'  : a'  : a Complementary CMOS Gates zPull-up network consisting of p-type devices zPull-down network consisting of n-type devices zExample: an inverter

CSE Autumn CMOS I - 10 abf abf a b  : a'b'  : a+b b a note that these are complements of each other CMOS NOR Gate zf(a,b) = (a+b)'

CSE Autumn CMOS I - 11 a c c a b f b General CMOS Gate  Use De Morgan's Law  :f(x)  :f'(x)  Example:f(a,b,c) = (ab+c)'  :(ab+c)' = (a'+b')c'  :ab+c

CSE Autumn CMOS I - 12 Complex Gates zAND-OR-Invert (AOI) for SOP zOR-AND-Invert (OAI) for POS zAny function without internal inversions f = a(b'+cd)

CSE Autumn CMOS I :1 a b f s f=a,when s=0 f=b,when s=1 f=s'a+sb Switch Logic vs. Gate Logic zExample: two-input multiplexer

CSE Autumn CMOS I - 14 complementary pass transistor Switch Logic vs. Gate Logic (cont'd) zTwo-input mux with gate logic (14 transistors) zTwo-input mux with switch logic (6 transistors)

CSE Autumn CMOS I - 15 F = AS 1 'S 0 ' + BS 1 'S 0 + CS 1 S 0 ' + DS 1 S 0 A B C D F S1S1 S0S0 Switches and Gates zAnother example: 4-to-1 multiplexor A B C D F S0S0 S1S1 sum-of-products form implementation with NAND gates 32 transistors + 4 for control

CSE Autumn CMOS I - 16 F S0S0 S1S1 A B C D F S0S0 S1S1 16 transistors + 4 for control 12 transistors + 4 for control 4:1 Multiplexor (cont'd) zUsing switch logic

CSE Autumn CMOS I - 17 A B C D F S0S0 S1S1 If A, B, C, and D are busses of many wires then the multiplexor structure will be replicated and should be made as small as possible even at the expense of extra control logic (it will only be needed once). 8 transistors 4:1 Multiplexor (cont'd) zMixed design

CSE Autumn CMOS I - 18 OR (ab)' a'b' abab (a  b)' Cin Cout G K P Exploiting Switch Logic zCarry-out of full-adder – implement with gates or switches

CSE Autumn CMOS I - 19 F A A' B B' C C' Bit0Bit1Bit2Bit3Bit4Bit5Bit6Bit7 Implementing Look-up Tables (LUTs) zMultiplexor logic – simple switch network (a tree) yinputs: programming bits ycontrols: inputs to CLB youtput: function value zHowever, series transistors are slow – O(n 2 )

CSE Autumn CMOS I - 20 Implementing Programmable Interconnect zSwitches connect wires at intersections zCan also be used to segment wire zRepeaters needed every so often ysimple non-inverting buffers (2 inverters) yotherwise, too many switches in series slow down signal