LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples

Digital Systems Digital system/circuit is any configuration of a circuit or System that processes or stores digital information. VHDL is a language that is developed specifically to model any digital system. Synthesis using tools/packages to analyze a circuit, enhance the design and transform it in a form that is downloadable in ASICs/FPGA and thus accelerating prototyping. The VHDL model is interpreted by software tools in such a way as to create actual digital circuits.

C-Based Hardware Design PC with C++ Application Implements Designs to Hardware Design and simulate at system level using C-based programming language such as Handel-C Need libraries that provide interface drivers including audio and video packages Need FPGA prototyping board, with variety of interfaces References: James Miller, Newsletter on Canadian’s System-On-Chip research Network, March 20, 2007, Vol. 5, No.1

Design Kit Output Targets Target a variety of FPGA’s Or convert Handel-C to: VHDL Verilog EDIF System C The output of the design kit can be down loaded to a variety of FPGAs or if you require some modification it can convert the Handel-C to other Forms such as VHDL…. Documentation and working Examples: https://www2.cmc.ca:ca/

Implementation is vendor English Prose Design Specification Transfer Function, Boolean Equations, Flow Graphs, Pseudo Codes Modeling the behavior VHDL Data Path Computational Units,Registers, Buses Logic Design Flip Flops, Gates, Netlist Transistors, Wires Masks Manufacturing Implementation is vendor dependent Netlist, ASCII text describing gates or library modules and their interconnection ASIC FPGA

VHDL Code of the Design Vendor’s Library VHDL Code of Test Design Verification Simulation Engine Synthesis is the use of software packages to automatically verify and translate the VHDL code into a targeted device, using embedded optimising methods and meeting all the design constraint. Synthesis is the process of interpreting the VHDL code and output the physical implementation of the circuit to be implemented on ASIC or programmed in an FPGA

FPGA Design Flow For Xilinx Virtex XCV50

Verilog Example // Description of a simple circuit . x B C y e   // Description of a simple circuit . module circuit_1 (A,B, C, x,y); input A,B,C; wire e; output x,y; and g1(e,A,B); not g2 (x,C); or g3(y,x,e); endmodule; x

//CMOS inverter module inverter (OUT, IN); input IN; output OUT; supply1 PWR; supply0 GND; pmos ( OUT, PWR, IN); // (Drain, Source, Gate) nmos (OUT, GND, IN); // (Drain, Source, Gate) end module   GND OUT PW R IN

For transmission gate the keyword cmos is used. cmos (output, input, ncontrol, pcontrol); // general description. For example for the transmission gate shown in the Figure below   cmos (Y,X,N,P);   x Y N P

The VHDL Language VHDL is a computer language with the set of syntax and usage rules. It is primarily used to describe hard ware and is a concurrent language. Introduced in 1985, standardized in 1987 modified in 1993. It is used mainly as a specification and modeling language for digital systems . It is also used as an intermediate form of design entry for many different tools It is also a simulation and verification language.

The Language VHDL is supported by DoD and most manufacturers. Technology Portable It is not yet standardized for synthesis. It has major applications in Rapid prototyping

VHDL DESIGN UNITS Entity Declaration Gives the interface view of the unit. Implementation Independent Architecture Describes the implementation(s) of the entity Package Declaration Contains global information common to many design units. Configuration Relates the design references to the designs saved in the library

BASIC CONSTRUCT entity OR_2 is -Input/output ports port -Interface entity OR_2 is -Input/output ports port (A, B : in BIT; Z : out BIT); end OR_2 ; --Body architecture DATA_FLOW of OR_2 is begin Z <= A or B; -- a construct statement implementing the OR gate end DATA_FLOW; Interface is responsible for defining the black box’s name, input and output Interface Body Body is responsible for describing the function that transforms the inputs to the outputs

Entity Organization Entity Interface Identifier, Generic constants, Port, Local types, signals…….. Architecture I Declarative Parts, Local signals, constants, types Concurrent statements Architecture n Declarative Parts, Local signals, constants, types Concurrent statements

Tutorials at http://www.encs.concordia.ca/helpdesk/resource/tutorial.html  

VHDL reserved words: They are identifiers reserved in the VHDL language for a special purpose. They cannot be used as explicitly declared identifiers. access after alias all and architecture array assert attribute begin abs block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded if in inout is label library linkage loop map mod new next nor not null of on open or others out package port procedure process range record register rem report return select severity signal subtype then to tansport type units until use variable wait when with xor

**VHDL is not case sensetive** Additional reserved keywords in VHDL-93 impure group inertia postponed pure literal reject rol ror shared sla sll sra srl unaffected xnor **All RESERVE WORDS ARE CASE INSENSETIVE** example: x_out <=A or B; X_Out<= a Or b; are acceptable statements **VHDL is not case sensetive**

--List of reserved operators = /= := < <= > >= + - * / ** & Equality operator Inequality operator The assignment operator for variables The “less than” operator “less than or equal to” when used in an expression on scalar types & array The assignment operator The “greater than” operator The “greater than or equal to” operator The addition operator The subtraction operator The multiplication operator The division operator The exponentiation operator The concatenation operator

Some notices VHDL is case in-sensative. Example: Z <=X and Y; are the same. VHDL is not sensitive to white spaces and tabs. Example: Z<= X and Y;  are the same. Parentheses used to clarify precedence. Example if x ='0'and y ='0'or z ='1' then statement if ( ((x ='0') and (y ='0')) or (z ='1') ) then

The Interface entity OR_2 is -- Input/output ports port keywords (reserved words) entity OR_2 is -- Input/output ports port (A, B : in BIT; Z : out BIT); end OR_2 ; the header name of the design (identifier) comment line Port declaration type type identifier optional terminates statements entity declaration

Identifiers Extended identifiers Case insensitive Characters can only be: First character must be a letter Last character must not be an underscore No adjacent underscores Make identifiers meaningful: Example My_COEN_6501_Project, OUT_1 Extended identifiers Any length Must be delimited by \ \ leading & trailing backslashes All graphic characters Within backslashes any characters in any order can appear (exception is backslash which has to appear in pair) Is case sensitive: An extended identifier is different from any keyword or basic identifier a – z A – Z 0 – 9 _ (underscore)

Port declaration port (A, B : in BIT; Z : out BIT); End of Reserved word port (A, B : in BIT; Z : out BIT); Predefined types Value of ‘0’ or ‘1’ End of Beginning of Keywords can be in out inout linkage buffer Information on direction of flow Any legal identifier Is a tri-state and bidirectional Is similar to out but is available within the architecture The VHDL compiler allows several port names to be included on a single line. Port names are separated by commas.

--Fundamental Data Types Values Example Bit Bit_vector Boolean Integer Real Time Character String ‘1’, ‘0’ (array of bits) True, False -20, 0, 1, 5090… 200.0, -2.0E2 10 us, 7 ns, 150 ps ‘c’, ‘z’, ‘5’, ‘#’, etc. (Array of characters) Q <= ‘1’; BYTE <= “00010101”; flag <= True; ACC <= ACC + 2; C1 = V2 * 5.3; output <= ‘0’ after 2 ns; DataOut <= ‘Y’; ADD <= “MEM” ;

The Body architecture DATA_FLOW of OR_2 is begin Z <= A or B ; Name of the architecture any legal identifier Association of architecture architecture DATA_FLOW of OR_2 is header header begin declaration part Z <= A or B ; Statement Part end DATA_FLOW ; Closes architecture Body declaration (architecture) optional

The operators Z <= A or B ; Signal assignment statement Logical operator Z <= A or B ; End of assignment do not forget the ; Assignment operator Signal assignment statement and or xor xnor nand nor not Other operators: *** “Anytime the input signal A and or B changes value the signal assignment statement executes and computes a new value for the output signal.” This is called “Signal Transformation.”

Concurrency Reserved word Concurrent assignment statement -- Interface ………… 1 entity XOR_2 is ……………… 2 Port ……………… .3 (A,B : in BIT; Z : out BIT); …………… 4 end XOR_2; ……………… 5 -- Body ………… …6 architecture DATA_FLOW of XOR_2 is …7 signal Sig 1, Sig 2: BIT; ……… 8 begin ………………9 Sig 1 <= A and not B; …………… ..10 Sig 2 <= B and not A; ………………11 Z <=Sig1 or Sig 2; ……………12 end DATA_FLOW; ……………13 Reserved word Signal Declaration Concurrent assignment statement

Modeling method Structural (A description of the entity by components instantiation) Behavioral Algorithmic (A description of the entity by the sequential statements) Data Flow ( A description of the entity by the use of concurrent statements) Mixed

Structural Synthesis behavioral Synthesis A C A C B B D D MUX MUX B B D D if t=0, then D<=0 else D<=DATA; CLK Control CLK Control

Configuration Statement It is used to bind the entity used with the architecture that is desired. Example: for all : OR_2 use entity OR_2 (data_Flow)

Libraries (Predefined) STD Provides declarations for predefined constructs in VHDL. WORK The working library into which design units are presently being analyzed are stored. (ie. design entities).

Libraries The design entities can be stored in libraries Libraries and their storage and implementation are achieved outside VHDL. VHDL is only the language that facilitates the usage of the libraries and its contents ie., the design entities. Any VHDL entity that can be analyzed is a COMPLETE DESIGN ENTITY * analysis means checking the syntax and symantic of a design entity statically. * simulate means checking the behaviour of the modelled entity dynamically. * There are two pre-defined libraries in VHDL: STD The standard IEEE library that holds many predefined types such as BIT. Many of these types are used almost like a reserved word because they are already predefined in the STD library. WORK This is the working library, where we store our currently analysed design entities

Standard Libraries The VHDL language has some standard libraries such as the IEEE Standard 1164 pack-age as well as some extentions. To take advantage of the main implementable feature of VHDL you need to import two main library packages Example: -- library declaration library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std. all;  There are other IEEE libraries, but they are not standardized, that you may use:

Structural Modeling Real Life Design and Implementation Structural modeling is the description of set of interconnected components that are previously defined, compiled and verified. Real Life Design and Implementation Design the board Design the chips Place sockets on the board Put the chips in the socket That is exactly how VHDL operates Design an entity that is the board Design the entities that are the chips You have components that are the sockets Design entities are put in the socket A VHDL STRUCTURAL Model interconnects the instances of chip sockets holding the chips.

architecture STRUCTURAL of CARRY is --Interface entity CARRY is port (A_IN, B_IN, C_IN : in BIT; C_OUT : out BIT); end CARRY; --Body architecture STRUCTURAL of CARRY is -Declaration of components component AND_2 port (A, B : in BIT ; Z : out BIT); end component ; component OR_3 port (A, B, C : in BIT ; Z : out BIT); end component; --Declare Signals signal TEMP1, TEMP2, TEMP3 : BIT ; begin -Connect Logic Operators to Describe Schematic A1: AND_2 port map (A_IN, B_IN, TEMP1) ; A2: AND_2 port map (A_IN, C_IN, TEMP2) ; A3: AND_2 port map (B_IN, C_IN, TEMP3) ; O3: OR_3 port map (TEMP1, TEMP2, TEMP3, C_OUT) ; end STRUCTURAL ; A_IN B_IN A_IN C_IN B_IN C_IN A1 A2 A3 TEMP1 TEMP2 TEMP3 OR1 C_OUT

DATA_FLOW CONSTRUCTS entity FULL_ADDER is port (A_IN,B_IN,C_IN : in BIT; SUM, CARRY : out BIT); end FULL_ADDER;   architecture DATA_FLOW of FULL_ADDER is signal S1,S2,S3: BIT; begin S1 <= A_IN xor B_IN; SUM <= S1 xor C_IN; S2 <= S1 and C_IN; S3 <= A_IN and B_IN; CARRY <= S2 or S3; end DATA_FLOW;

AND Gate simulation

Passgate simulation

library ieee; use ieee.std_logic_1164.all; entity Full_Adder is -- generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X, Y, Cin: in std_logic; Cout, Sum: out std_logic); end Full_Adder; architecture Concurrent of Full_Adder is begin Sum <= X xor Y xor Cin after 0.11 ns ; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 0.11 ns; end Concurrent;