Mark Raymond - 5/10/061 TFB hardware status – 5/10/06 update including mods discussed at previous meeting (7/9/06) connectors (power and signals) LV power HV switch LM92 temperature monitoring layout status and ECAL mounting timescale

Mark Raymond - 5/10/062 power connector 20 way, dual row, 0.1” pitch MOLEX connector, 3A/pin rated HV HVgnd 1.2gnd 2.5gnd 3.3gnd 5gnd some questions (some answers) who provides the cabling – do we make it ourselves? someone else 48 TFBs per power group – how/where do we split the incoming power lines to feed individual TFBs? at a distribution module how can we make use of regulator shutdown to disable individual TFBs? can’t fuses? (regulators include overcurrent/overtemperature protection) could fuse at distribution module? Shorted SiPM will draw HV current but series resistance will limit to < 1mA can switch off HV (to whole board) and monitor HV current voltages after regulation – actual incoming levels will be higher use 2 pins/supply

Mark Raymond - 5/10/063 signal connectors data screened RJ twisted pairs data in data out 100 MHz clock triggering line (spill start, spill no., cosmic, calibration?) trigger out only one twisted pair/TFB needed use second RJ45 but only one pair merge signals into RJ45 cable to GTM using an intermediate board

Mark Raymond - 5/10/064 TFB onboard LV power regulators supplyafter reg.component current [A]circuitry supplied power on TFB [W] LP38843ES-1.2< 3FPGA core A<0.5trip-t LP3856ES D~1.05FPGA DLP3856ES-ADJ~0.95FPGA I/O ALP3856ES-5.0<0.2ADCs / HVtrimDACs return14.7 all TO263-5 packages (not proposing to use shutdown I/Ps) two other small regulators on board to supply PROM (1.8V), slow control cct. (precision 5V), but low power requirements and can take inputs from above supply levels dropout depends on current – should prob. take worst case incuding regulator power (hopefully worst case)

Mark Raymond - 5/10/065 HV switch HV in HV on TFB (to all SiPMs) FPGA GND 100k 1M 47k 1M 47k 100 ohms 100k ADC I/P 0.1uF BSP225 BSS131 prototyped and works OK monitor HV either side of 100 ohms -> crude current measurement 1mA -> 100mV, but resistive division -> only 5mV difference at ADC I/Ps (ADC resolution 1.2 mV) go with this for now, but maybe DC-DC conversion on TFB possible?

Mark Raymond - 5/10/066 LM92 temperature sensor SO8 SDA SCL T_CRIT_A GND VS A0 A1 INT I2C bus up to 4 I2C addresses (one on board – 3 ext.) 3.3V active when T outside programmable window acitve when T > programmable limit +/ deg. accurate around 25 deg. region can mount on small external PCBs for up to 3 external monitoring points 6 wire connector for IDC cable (3.3/GND/SDA/SCL/T_CRIT_A/INT) now on TFB T_CRIT_A and INT open drain so connect all devices in parallel to 2 FPGA I/Ps

Mark Raymond - 5/10/067 slow control (monitoring) single channel AD5321 DAC 0 -> 5V, 12 bit resolution, for trip-t electronic calibration 8 channel AD7998 ADC, 0 -> 5V (power and Vref provided by REF195), 12 bit resolution both chips with I 2 C interface controlled by FPGA allocation of AD7998 inputs 11.2V supply 22.5V supply 33.3V supply 45V supply (divided down) 5HV before 100 ohms (divided down) 6HV after 100 ohms (divided down) 7front end cal voltage 8spare

Mark Raymond - 5/10/068 TFB PCB layout status coaxial connectors on top surface trip-t, FPGA, HVtrimDACs on bottom (can be thermally coupled to cooling) ADCs, regulators, connectors on top surface I2C connector for external temperature sensors (up to 3) 6 routing layers top, bottom + 4 internal + power and ground layers so maybe 10 layers overall? signal routing complete work still to do power and ground planes board is now 16 cm in the long direction, 9cm in the short 2 RJ45’s

Mark Raymond - 5/10/069 cooled Al mounting plate thermal gap filler TFB TFB mounting for ECAL TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed min. coax connectors (and other connectors) on top surface chips to be cooled on bottom surface, in thermal contact with plate thermal gap filler allows for differences in chip thicknesses power regs. on top side – dissipating heat to board – so will need to provide good thermal pathway to mounting plate in this area of TFB to SiPM coax socket ~2 mm dia. terminated coax cable (1.3 mm dia.)

Mark Raymond - 5/10/ cm 9 cm power data + trig. cutouts to feed mini- coax’s thru to SiPMs TFB mounting for ECAL 6 x 3mm mounting holes

Mark Raymond - 5/10/0611 timescale still ~1-2 weeks work left on layout most components procured for up to 25 boards only FPGA and PROM (both BGA) non RoHS compliant => 2 step manufacture process still plan to produce 2 boards quickly - hopefully by ~ end October produce more, on slower timescale, after no major (electrical) problems identified testing needs some thought….

Mark Raymond - 5/10/0612

Mark Raymond - 5/10/0613 Trip-t and TFB status Trip-t brief description of internal architecture and interfaces proposed Trip-t operation at T2K SiPM connection, gain and discriminator threshold considerations Results from latest Tript version linearity and discriminator measurements TFB prototype status results from prototyping elements ADC functionality and test results HVtrim functionality and test results Calibration circuitt description and test results TFB layout status TFB firmware status future plans DRAFT TALK – NOT YET FINISHED

Mark Raymond - 5/10/0614 Trip-t single channel front end architecture preamp very simplified – neglecting features not relevant to ND280 operation integrate/reset gain 1 or 4 gain adjust 1,2,3,…8 x10 Vth analogue pipeline disc. O/P Qin only preamp gain affects signal feeding discriminator – no fine control (x1 or x4) Vth common to all channels on chip analog bias settings, gain, Vth, programmable via serial interface discriminator 1pF 3pF reset

Mark Raymond - 5/10/0615 Trip-t full chip 32 channel chip -> 1 serial output, 48 deep analogue pipeline to store sampled front end outputs (note: pipeline operated using 2 timeslices/preamp integration period, so length reduced to 23 see for detailed explanation) have to select either top or bottom 16 disc. O/Ps to transmit off-chip ~ 12 digital control/programming inputs, 16 disc. outputs => ~ 30 I/O lines/chip (2.5 V CMOS) 32 front end chans top 16 IP/s bottom 16 I/Ps analogue memory (pipeline) analog outputs top 16 disc. O/Ps bottom 16 disc. O/Ps top or bottom 16 disc. O/Ps 32 32:1 analog MUX serial analog output dig.MUX 32:16 bias, control, reset control serial programming interface, bias gen., control interface, … dig.control simplified and neglecting features not relevant to operation in ND280

Mark Raymond - 5/10/0616 Proposed mode of Trip-t operation for beam spill data acquisition is as follows during spill integrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches) timestamp high gain channel discriminator outputs that fire after spill continue running in same way, for a while, to catch late signals (  decay) readout entire contents of pipeline assemble data block containing hit timestamps and all digitized analogue data and transmit transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gain vast majority of data is pedestal + single/double p.e. hits only Trip-t operation at T2K 5.25  s spill period 2.8  s after spill active period 74  s (23 cell) readout period (if O/P mux running at 10 MHz) start of spill end of spill at this time trip-t switches to inter-spill operational mode (cosmic trigger)

Mark Raymond - 5/10/0617 Tript for ND280, gain considerations need ~ 500 p.e. dynamic range, while simultaneously discriminating signals at the ~ 1p.e. level can’t be done with one gain range => split signal between high/low gain ranges (channels) Signal shared between Cadd, Chi and Clo (also some strays), Chi/Clo = high/low gain ratio HVglobal 1 M  50  thin coax SiPM trip-t Chi 100pF Clo 10pF Cadd 330pF HVtrim Choose Cadd to match final SiPM gain (330pF about right for 5x10 5 ) Cadd also helps with gain discontinuity when hi gain channel saturates (see don’t know what final SiPM gain will be, but assume production devices will be quite well matched in any case will have individual channel gain adjustment by HVtrimDACs simplified single SiPM channel schematic

Mark Raymond - 5/10/0618 Discriminator threshold (Vth) considerations x10 1pF reset Vth disc. O/P analogue pipeline Qin Vth only relevant to the 16 high gain channels - remember only 16 channels can be selected for transmission off-chip, so just arrange for these to be the high gain channels (Vth also applied to low gain channels, but we don’t need to look at the outputs of these) Vth needs to be set high enough to prevent single p.e. events triggering discriminator (otherwise single p.e. triggers will dominate and will lose ability to timestamp real signals) uncertainty in threshold setting given by spread in discriminator turn-on curves across chip can choose high gain channel value (external capacitor division ratio) but trade-off between threshold adjustment range and uncertainty in threshold value

Mark Raymond - 5/10/0619 x10 1pF reset Vth disc. O/P analogue pipeline Qin ~ 1V dynamic range available at preamp O/P ~ similar voltage range at x10 amp O/P ~ similar disc. thresh. voltage adjustment range 2.5 V CMOS so can assume dynamic ranges of internal circuits ~ 1V this has implications for discriminator threshold range if want 0 – 5 p.e. adjustment range then 5 p.e. ≡ 1V at x10 O/P => 1V ≡ 50 p.e. at preamp O/P so high gain channel will saturate at ~ 50 p.e. this translates to threshold uncertainty ~ +/- 0.5 p.e. (measured – see later) Gain and gain ratio considerations (1) single tript channel

Mark Raymond - 5/10/0620 So discriminator threshold range adjustment 0 -> 5 p.e. High gain channel saturates at 50 p.e. Choose Chi/Clo so low gain channel saturates at 500 p.e. Note: These values are examples and can change, but need to take care with threshold adjustment range/uncertainty trade-off Gain and gain ratio considerations (2) HV(TFB) 1 M  50  thin coax SiPM Trip-t Chi 100pF Clo 10pF Cadd 330pF HVtrim simplified single SiPM channel schematic

Mark Raymond - 5/10/0621 Latest Trip-t test results from final version 2 nd (final) tript version very similar to 1 st minor architecture change to improve O/P stage linearity version 2 linearity clearly better but still some gain reduction for small signals  will need electronic calibration to correct for linearity

Mark Raymond - 5/10/0622 Tript V2 linearity(1) all 16 channels, hi and lo gains component values chosen for SiPM gain ~ 5x10 5 (Chi = 100pF Clo=10pF, Cadd=330pF) lo gain saturates at ~ 40 pC (500 p.e.) hi gain saturates at ~ 4 pC (50 p.e.) higain cahnnels logain channels

Mark Raymond - 5/10/0623 Tript V2 linearity(2) log-log plot of same data 10:1 gain ratio means gain range change occurs where logain signal size already large so no S/N problems higain channels logain channels

Mark Raymond - 5/10/0624 Tript V2 discriminator measurement count the no. of times the discriminator fires for 1000 preamp integration periods sweep the injected signal size for 5x10 5 1p.e. -> 0.08 pC pk-pk width ~ 1 p.e. also for this measurment so +/- 0.5 p.e. precision can improve precision but remember trade-off with adjustment range 1 p.e. discriminator curves for all 16 higain channels 2 p.e.

Mark Raymond - 5/10/0625 Tript V2 discriminator timewalk p.e. (1 p.e. = 80 fC (5x10 5 ) significant timewalk and chan- to-chan spread for small signals can set threshold at 1.5 p.e. and discriminator will fire, but timestamp for low amplitude signals will not be reliable OK for signals > ~ 3 p.e. can correct for timewalk off-line

Mark Raymond - 5/10/0626 TFB (Tript Front-end Board) prototype status main functionality: 4 Tript’s/TFB => 64 SiPM channels (for ECAL) individual programmable HVtrim (5 V range) for each SiPM channel tript O/P signal digitisation front end electronic calibration FPGA to program tript, sequence operation, timestamp hits, control digitisation, format and transmit data, … local LV power regulation prefer to prototype designs for individual functions as much as poss. before committing to final TFB prototype results here for on-board ADC, HVtrim and electronic calibration circuits

Mark Raymond - 5/10/0627 cal cct HVtrimDAC AD9201 SiPM Tript miniature coax and connectors prototyping elements of TFB necessary to proove as much of TFB circuitry as possible before committing to layout helps to identify where extra layout care is needed improves chances of TFB prototype working successfully

Mark Raymond - 5/10/ k 50V, pF 50V pF 100V pF 100V pF 100V R LV nF LV k LV, 0402 trip-t 10pF 100V, 0603 HVglobal HVtrim(0-5V) cal test pulse coax sheath not DC coupled to GND SiPM SiPM -> TFB connection - details 47k 50V, 0402 HVglobal: common to all SiPM channels on TFB HVtrim: individual for each SiPM channel, 5V adjustment range (choice of 8/10/12 bit DAC precision) HVtrim applied to coax sheath – AC but not DC coupled to GND significant no. of passives/channel – need careful, high density layout

Mark Raymond - 5/10/0629 ADC for the TFB AD9201 – used by D-zero dual-channel => 2 tript’s/ADC 28 pin SSOP package separate analog and digital supplies 5V analogue – needed to accommodate tript O/P range 3.3 V digital

Mark Raymond - 5/10/0630 analog supply and ADC reference voltage configuration optimised so that tript output signals well matched to 10 bit ADC range tript linearity measured with AD9201

Mark Raymond - 5/10/0631 SiPM signals measured with tript/AD9201 Russian SiPM: gain 5.6x ns preamp integration period 100,000 events in each spectrum ~ 10 ADC units / p.e. => 0.1 p.e. ADC resolution

Mark Raymond - 5/10/0632 HV trim circuit for TFB 51R LV nF LV k LV, 0402 HVtrim(0-5V) coax sheath carries HVtrim voltage SiPM HVglobal 8 channel DAC chip => 2 / tript, 8 / TFB 8/10/12 bit versions available identical chips, just different resolution (price difference but negligible to us) TSSOP 16 pin SM package serial interface to program (from FE FPGA) output voltage variable 0 -> 5 V 20 mV resolution for 8 bit version

Mark Raymond - 5/10/0633 TFB HV trim circuit linearity 8 bit DAC version used here gives 20 mV precision for 5 V range should be enough? single DAC channel measurement

Mark Raymond - 5/10/0634 TFB HV trim circuit with SiPM SiPM LED spectra for device with nominal 47.5 V operating voltage showing effect of HVtrim circuit 5 Volt range for HVtrim gives overall range 45 – 50 Volts (when combined with HVglobal)

Mark Raymond - 5/10/0635 CAL circuit for TFB Vcal (0 – 5 V) (use another AD5308 DAC here) to 16 trip-t SiPM channels before gain splitting capacitors 4 CAL lines feeding every 4 th channel from FE-FPGA discrete MOSFETs 10 pF

Mark Raymond - 5/10/0636 CAL circuit test results with tript/AD low gain chans 16 high gain chans tript multiplexed analog output stream for different DAC values for one CAL test input – sampled with scope tript MUX (and ADC) running at 5 MHz substantial crosstalk – but only after high gain channels beyond saturation

Mark Raymond - 5/10/0637 CAL circuit test results with tript/AD9201 linearity measured for one SiPM channel using external test pulse and CAL circuit -> close correspondence (also using AD9201)

Mark Raymond - 5/10/0638 TFB elements prototyping summary tript output ADC, SiPM HVtrim DAC circuit and electronic chain calibration circuit all prototyped and tested no major problems encountered can now proceed to lay out the TFB prototype with confidence that at least these elements should function OK.

Mark Raymond - 5/10/0639 Tript FPGA footprint HVtrim 16 SiPM I/Ps and passives CAL cct AD9201 footprint TFB layout status – 10 cm x 16 cm high density SiPM I/P layout complete – gives confidence that size target ~ achievable still much left to do (e.g. FPGA dig. signals routing, power regs., connectors (power and control), slow control interface, …..

Mark Raymond - 5/10/0640 cooled Al mounting plate thermal gap filler TFB TFB mounting ideas (ECAL) TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed min. coax connectors (and other connectors) on top surface chips to be cooled on bottom surface, in thermal contact with plate thermal gap filler allows for differences in chip thicknesses power regs. on top side – dissipating heat to board – so will need to provide good thermal pathway to mounting plate in this area of TFB to SiPM coax socket ~2 mm dia. terminated coax cable (1.3 mm dia.)

Mark Raymond - 5/10/0641 TFB interfaces 4 LVDS pairs (RJ45 type connector and cable – should be screened) Clocks input:100 MHz, 1Hz, Spill/Cosmic trigger Data input Data output RF clock ? (maybe not needed) slow control TBD (maybe just a connector to plug-on micro-controller based circuit?) Power < ~100VsmallSiPM HV +2.5~ 0.5A tript and FPGA I/O + 5 ~ 0.2AADC analogue and HVtrim DAC +3.3 TBDADC digital and FPGA I/O +1.2TBDFPGA core

Mark Raymond - 5/10/0642 for programming tript: ~ 900 kbits for 50k channels HVtrim DACs: 8 bits res’n x 50k chans = 400 kbits for raw spill data readout (data only) assume 23 integration periods 4 tript’s / TFB 32 channels/tript (hi and logain) 10 bit ADC => ~30k bits /TFB /spill + hit timestamp data and associated hit channel addresses some data volume numbers

Mark Raymond - 5/10/0643 planning Plans for this year (2006) 1 st TFB prototype to be produced by end October in parallel produce sufficient firmware for characterization detailed electrical characterization by beginning 2007 Plans for next year (2007) vertical slice test (1 st quarter) TFB prototype with photosensors, RMM and MCM prototypes review requirements and design 2 nd (final) TFB prototype for ECAL produced and tested by end of year