14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 1 Backend Preliminary Functional Design

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 2 Monitor And Control Processor Data Processing Processors e2e CorrelatorM &C Backend Data Processing Processors Data Processing Processors BACKEND CLUSTER ORGANIZATION Monitor And Control Processor

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 3 Backend Control Backend Monitor Output DP Input M & C Correlator e2e Backend HWSW Major Functions

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 4 Input Output Input Cache Manager Five DP Node Processes, Control And Data Flows Input Cache Output Cache Processing Output Cache Manager

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 5 Receive Data Update Cache Address Cache Full ? No Yes Input Process (discard)

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 6 Input Provides Large Memory Area for Depositing Incoming Lag Frame Data Signals When Segment is Full Immediately Moves to Next Segment Discards New Input When Memory is Full Bare Minimum Overhead

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 7 Input Cache Three Shared Memory Data Structures Accessible by Input, Input Cache Manager and DP Processes Input Cache Lag Frame Store Cache Segment List Lag Set Tables

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 8

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 9 Lag Frame Store Written only by Input Process Read by Input Cache Manager and DP Processes Divided into a Limited number of Large Segments Input Writes to Entire Segment at One Time

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 10 Lag Set Number Skip Count Lag Count Lag Frame Indices N+3 N+2 N+1 N SEGMENT LIST Segment Number Frame Count LAG SET TABLE K K+1 K Integration Block ( 8 lag frames X 128 lags per frame = 1024 lags per lag set )

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 11 Segment List Contains Status Data (Frame Count) on Lag Frame Store Segments Written by Input and DP Read by Input, Input Cache Manager and DP Frame Count Value of Zero Means Available for New Input Non-Zero Status Means in DP or Awaiting DP

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 12 Lag Set Table Sorted Addresses of Lag Frames Making-up a Single Lag Set Written Only by Input Cache Manager Read Only by DP Integration Block, Skip Count and Lag Count Auxiliary Data Columns

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 13 Lag Set Table Integration Block Identifies all Lag Sets in the Same Integration Sequence Skip Count Registers Number of Times a Lag Set has been Passed by Lag Count Maintains a Record of the Number of Indices That Have Been Sorted into the Table

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 14 Input Cache Manager Reads Lag Frames From Lag Frame Store Updates Lag Frame Index Entries in Lag Set Table Updates Lag Set, Lag Count Entries Monitors Number of Segments Available for Input

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 15 Retrieve Lag Set DP Pipeline Check for Message Clean-up Max Skips ? Data Processing Loop Yes No

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 16 Data Processing Overview Read Lag Frames Using Lag Set Table Indices Check for Availability of Auxiliary Data DP Pipeline Incoming Message Check Clean-up of Skipped Lag Sets

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 17 Lag Frame Read Access Only Lag Sets with Full Lag Counts Access Only Lag Sets with Available State Counts Lag Frame Index Points to Lag Frame Store Location Indices Are In Order of Assembly Increment Skip Count for Those That Do Not Yet Qualify

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 18 Normalization Time Stamp Adjust Fourier Transform Integration Processing Pipeline Detail Error Trap/Recovery Input Cache Output Cache Other Time Domain Proc Freq Domain Processes

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 19 DP Pipeline Apply Normalization Update Time Stamps (Recirculation) Possible Additional Time Domain Applications Fourier Transform (Complex- Complex, Power of 2 FFT) Possible Frequency Domain Applications Accumulate Move to Output Cache

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 20 Incoming Messages Mode Change State Counts Shutdown/Resume Always Received From BE Control

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 21 Cleanup Periodic Check of Skipped Lag Sets Process Those That are Now Ready Increment Skip Count for Those That are Still Not Ready Discard Those That are Too Old (Rare)

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 22 Output Cache Shared Memory Array Disk Backup for Paging Accessible by DP, Output and Output Cache Manager Processes

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 23 Output Cache Manager Receive Request Send Index To DP Send Index To Output Check Cache Status Page-in / Page-out

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 24 Output Cache Manager Receive Cache Index Request From DP Return Address of Next Free Location Receive Cache Index Request From Output Return Address of Next Data Going to e2e

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 25 Output Cache Manager Page-out Data When Memory Gets Full Page-in Data In Anticipation Of Retrieval for Output

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 26 Output Function Format Retrieve from Cache Send Data Check Send ok Wait on Processing Not ok Cache Empty Output Cache e2e

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 27 Output Obtain Output Cache Index From Output Cache Manager Fetch Data From Output Cache Format Send to (Deposit into) e2e Archive

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 28 Backend Control Processors Monitor Backend M & C Functions Processes Monitor Network Monitor Operating Environment

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 29 BE Control Message Intermediary Among BE Processes and M&C Three Classes of Incoming Messages Maintains Statistical Model of BE State

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 30 BE Control Class I Messages are Simply Routed to Proper Destination Class II Messages are Read for Updates to the Statistical Model and Routed to Proper Destination Class III Messages are Used to Generate Check and Repair, and Offload Requests

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 31 BE Monitor Status Checks Internal Network Restart Processor Reboot Process Kill and/or Restart Offload Failure, Error, Warning, Repair, Status, Offload Reports

14-15 May,2002 EVLA Correlator Backend Functional Design Tom Morgan 32 Development Schedule 2Q 2002 – 4 Node Test Cluster 3Q 2002 – 8+ Node Cluster 4Q 2002 – Functional Prototype 4Q 2003 – Full Functionality 3Q 2004 – First Prototype Correlator Boards 4Q 2004 – Earliest BE Connect to Correlator Hardware