ECE 465 Introduction to CPLDs and FPGAs Shantanu Dutt ECE Dept. University of Illinois at Chicago Acknowledgement: Extracted from lecture notes of Dr. Mohamed M. Elkhatib, German University of Cairo and Prof. Russell Tessier, Univ. of Massachusetts. Some modfications and additions done by Prof. Dutt.

CPLD Families

CPLD Block Diagram Function block (~ PLA w/ 1 o/p that can be FF’ed) Programmable switch for interconnecting various FBs FF I/Ps O/Ps Crossbar Switch An individual switch In a crossbar is a diamond switch

CPLD Function Block PLA-like AND array Literal inputs (e.g., a, b, c) Extra function (e.g., g, h) i/ps for OR term Example function f= ab+bc’+g+h D-FF 2:1 Mux

Field Programmable Gate Arrays (FPGAs)

FPGA Types (Anti-fuse technology)

FPGA Families

PSM: Programmable Switch Matrix (for making connections between interconnects of different channels). The structure shown only allows i-to-i connections CLB: Configuration Logic Block (programmable logic cell) Horizontal routing (interconnect) channel Vertical routing channels SRAM-type FPGA Interconnect Architecture Diamond switch

SRAM-type FPGA Interconnect Architecture (contd) PSM Cell Connection Matrix (CCM)

Configuration Logic Block (CLB) 5-i/p function implemented using G, F and H LUTs (Look Up Tables) using Shannon’s Expansion: p(a,b,c,d,e) = a p(1, b, c, d, e) + a’ p(0, b, c, d, e) = a q(b,c,d,e) + a’r(b,c,d,e). q( ) impl. using LUT G, r impl. using LUT F and p=ag + a’h impl. using LUT H The LUT o/ps can go through a FF (for seq. ckt design) or bypass it for a combinational o/p This is called technology mapping: mapping the logic to CLB logic components

Technology Mapping

Programming a CLB (contd)

Components of Modern FPGAs

Digital System: Implementation Spectrum –ASIC gives high performance at cost of inflexibility. –Processor is very flexible but not tuned to the application. –Reconfigurable hardware is a nice compromise. MicroprocessorReconfigurable Hardware ASIC Software Firmware Hardware

Simplified FPGA Logic Element

High-level Compilers & FPGAs –Difficult to estimate hardware resources. –Some parts of program more appropriate for processor (hardware/software codesign). –Compiler must parallelize computation across many resources. –Engineers like to write in C/VHDL/Verilog rather than pushing little blocks around. for (i = 0; i<n, i++) { c[i] = a[i] + b[i] } Some success stories

Translating a Design to an FPGA –CAD to translate circuit from text description to physical implementation well understood. –Most current FPGA designers use register- transfer level specification (allocation and scheduling) –Same basic steps as ASIC design. RTL. C = A+B. Circuit A B +C Array

Circuit Compilation & Implementation: Basic Steps 1.Technology Mapping 2.Placement 3.Routing LUT ? Assign a logical LUT to a physical location. Select wire segments and switches for Interconnection. 4. Convert all implementation “details” to FPGA programming info (configuration bits): LUT RAM bits, CCM & PSM FF/SRAM bits, etc. Can store config bits on disk or ROM and load into FPGA as needed Can thus use the FPGA to implement multiple digital systems (at different times or sometimes simultaneously in different FPGA partitions)

Technology Mapping: A Simple Example FA AB CoCo CiCi S Made of Full Adders A+B = D Logic synthesis tool reduces circuit to SOP form C o = ABC i + ABC i + ABC i + ABC i S = ABC i + ABC i + ABC i + ABC i LUT CoCo CiCi B A S CiCi B A

Processor + FPGA 1. FPGA serves as coprocessor for data intensive applications – possible project. Three possibilities Backplane bus (e.g. PCI) Proc chip daughtercard FPGA chip FPGA Proc 2. FPGA serves as embedded digital system for lower latency processing. “Reconfigurable Functional Unit”