Hartman1P1004 Leo Hartman Canadian Space Agency A VHDL Implementation of an On-board Autonomy Solution

Hartman2P1004 Overview Summary of goal decomposition hierarchy (GDH) Pipeline implementation of GDH Performance Future work

Hartman3P1004 C GDH Structure A B Primitive operation Serial decomposition A B Parallel decomposition Activation condition Value parameters pass information to subgoals. Stream parameters pass information between subgoals in real-time, i.e., shared memory. C Subgoal Alternative decompositions Activation passes downward to decompositions and subgoals. When a goal becomes active, the first decomposition whose activation condition is true becomes active. Success and failure propagate upward. A goal decomposition hierarchy is evaluated by cyclic execution of the active decompositions and subgoals. If an activation condition becomes false, the node fails.

Hartman4P1004 On-board environment Xiphos Technologies' Q-card Goal decomposition hierarchy Higher level applications: health monitoring resource tracking payload operations Spacewire networking

Hartman5P1004 Still active goals GDH Execution Behavior Execution pipeline Successful Goals Failed Goals Active Queue Active goals

Hartman6P1004 GDH Hardware Overview Memory GDH Pipeline FIFOs Parameter updating Active queue handler Fetching data structures Parameter fetching & initialization

Hartman7P1004 Active Queue Handler Keeps track of active goals in a set of synchronized FIFOs Provides and records references to active goals' data structures Controls the queue FIFOs that give each goal a turn to be processed in the pipeline

Hartman8P1004 Active Queue Handler and FIFOs Active Queue Handler Goal Address Goal State Info Copy Parent State Info Copy Unused Addresses for Copies Goal Parameters Parent Parameters Unused Addresses For Parameters Control signals Data exchange Goal Info to Pipeline

Hartman9P1004 Pipeline register Stage X Combinational Logic or High Speed State Machine Flow control : clock, freeze, etc. GDH Pipeline Pipeline register Stage X Combinational Logic or High Speed State Machine Pipeline register

Hartman10P1004 FIFOs & Memory Allocation Goal Address FIFO Goal State FIFO Parent Goal State FIFO Unused Addresses FIFO Goal Parameters FIFO Parent Goal Parameters FIFO Unused Addresses FIFO

Hartman11P1004 FIFOs & Memory Allocation Data Structure Off- Chip Memory Goal State Info Memory Parameter Values Memory Parameter Addresses Memory

Hartman12P1004 Conclusions Functional pipeline without parameters. Routed synthesis: state machines at 150Mhz for a total processing speed ~10Mhz. Synthesized modules take 10% to 15% of a 1M cell FPGA (Xilinx Virtex II)

Hartman13P1004 Future Work Complete pipeline implementation by including parameters and user-defined circuits for activation and primitive operations. Memory initialization & GDH IDE. Explore other approaches for GDH hardware implementation.