Henok Abebe Collaborators MOSIS Compact Modeling for Symmetric and Asymmetric Double Gate MOSFETs Henok Abebe The MOSIS Service USC Viterbi School of Engineering Information Sciences Institute Collaborators Ellis Cumberbatch and Hedley Morris: CGU School of Mathematical Sciences, USA Vance Tyree: USC/ISI MOSIS, USA Shigeyasu Uno: Nagoya University, Department of Electrical and Computer Engineering, Japan 1st International MOS-AK Meeting, co-located with CMC Meeting and IEDM Conference, Dec.13 2008, San Francisco, CA

Outline 1-D symmetric undoped DG MOSFET modeling. MOSIS Outline 1-D symmetric undoped DG MOSFET modeling. 2-D asymmetric and lightly doped DG MOSFET modeling. Mid-section electrostatic potential approximation. Long channel mobile charge and current models for asymmetric DG MOSFET. Preliminary simulation results and comparison with numerical 2-D data.

1-D symmetric undoped DG MOSFET modeling MOSIS 1-D symmetric undoped DG MOSFET modeling Undoped and symmetric. Relatively small silicon thickness (eg. tsi=5nm). Two gate voltages are taken to be the same. Thin gate oxide (eg. tox=1.5nm).

1-D symmetric DG (continued) MOSIS 1-D symmetric DG (continued) Boundary conditions Poisson equation

1-D symmetric DG (continued) MOSIS 1-D symmetric DG (continued) Exact solution using the first two boundary conditions: Surface potential:

1-D symmetric DG (continued) MOSIS 1-D symmetric DG (continued) Interface boundary condition equation for β:

1-D symmetric DG (continued) MOSIS 1-D symmetric DG (continued) Total mobile charge per unit gate area: Channel current:

Summary of the 1-D symmetric DG MOSFET MOSIS Summary of the 1-D symmetric DG MOSFET For charge and current calculations, equation needs solving at source and drain only. Have efficient iteration algorithm to solve for Results are very accurate (see WCM proceedings Vol. 3, pp. 849,  June 1-5, (2008), Boston)

2-D asymmetric and doped DG MOSFET modeling MOSIS 2-D asymmetric and doped DG MOSFET modeling Scaling

2-D asymmetric (continued) MOSIS 2-D asymmetric (continued) Parabolic potential approximation:

2-D asymmetric (continued) MOSIS 2-D asymmetric (continued) Boundary conditions:

2-D asymmetric (continued) MOSIS 2-D asymmetric (continued) Surface potentials: Explicit solutions can be calculated for wsf and wsb.

Mid-section electrostatic potential approximation MOSIS Mid-section electrostatic potential approximation Long channel approximation:

Mid-section (continued) MOSIS Mid-section (continued)

Long channel mobile charge and current models for asymmetric DG MOSFET MOSIS Long channel mobile charge and current models for asymmetric DG MOSFET Total mobile charge per unit gate area: Channel current:

Preliminary simulation results and comparison with numerical 2-D data MOSIS Preliminary simulation results and comparison with numerical 2-D data Mid-section potential versus relative gate voltage and relative surface potential with 5nm silicon thickness (lightly doped asymmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Mid-section potential versus relative gate voltage and silicon thickness with 1.5nm oxide thickness (lightly doped symmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Channel current and output conductance versus source-drain voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Channel current and tansconductance versus gate voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Channel current and output conductance versus source-drain voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Channel current and tansconductance versus gate voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Channel current and output conductance versus source-drain voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

Preliminary simulation (continued) MOSIS Preliminary simulation (continued) Channel current and tansconductance versus gate voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

University of Southern California (USC) Viterbi School of Engineering Information Sciences Institute (ISI) The MOSIS Service Marina del Rey, California MOSIS