M. Labiche - INTAG workshop GSI May Se - D prototype for the focal plane of the PRISMA spectrometer (Task4) Digitisers for SAGE & LISA (task1)

M. Labiche - INTAG workshop GSI May Se - D prototype for the focal plane of the PRISMA spectrometer (Manchester, Daresbury, Paisley EPSRC grant) Detector: – Principle (see Ivan Mikka ’ s talk) – Prototype at Manchester Electronics – ASIC’s + FADCs

3 Motivation Z, A identification for medium mass and heavy nuclei

4 Prototype at Manchester University - Aluminized mylar emissive foil (~.9µm thick) - MWPC with 64 wires - with individual wire readout

5 Prototype SED PPAC readout Gassiplex 16 channel ASIC Preamp – Shaping amp – Track and hold Analog multiplexed output Two GAS32 boards – 64 PPAC wires – four connections. 5Mhz readout clock – 14us 10 ADC samples per channel – average of four recorded. PowerPC in the FPGA formats data Currently slow serial link to MIDAS in PC – 100hz event rate. Ethernet is in development The EDAQ readout system From P. Coleman-Smith

6 Existing ASICS chips : Gassiplex (Gas32) Two Gas32 cards (with 2x16 Gassiplex ASICs per card) reading 64 PPAC wires in place behind the MWPC. ASICs

7 Eight channel FADC - ASIC readout module in the laboratory during development Flash ADCs module

8 Test of the FEE prototype at Daresbury Lab. 1 Gas32 card connected to a 16x2 strips DSSD 3-  source used The FEE prototype performed well

9

10 Gaseous detector 64 output channels

11 - Two GAS32 boards are installed in the chamber to read 64 wires from the gaseous detector. - The V4FADC and data acquisition equipment is installed in Manchester for use with the SED prototype. - VME readout of a second MWPC installed into the same data acquisition system. - Ten further V4FADC modules have been manufactured by Norcott Engineering. Commissioning will be carried out by P.J. Coleman-Smith. In summary :

M. Labiche INTAG workshop GSI May Digitisers for SAGE & LISA Detector SAGE & LISA: Digitisers + TDR interface

13 Silicon And Germanium array (SAGE) (Liverpool, Daresbury EPSRC grant) For spectroscopy of heavy nuclei SAGE will be used to detect in coincidence the electrons and photons at target position of RITU.  SAGE sensitive to both E2 and M1 transitions SAGE : Jurogam + SACRED

14 Light Ion Spectroscopy Array (LISA) (Liverpool, Surrey, Daresbury EPSRC grant) For proton drip line spectroscopy (in the region N=Z) LISA = Si detector at target position of RITU to detect prompt charged particles (protons or alphas). LISA design: Resis. strip octagonal detector + annular DSSD at forward angles

15 Digital Electronics Requirements: 14bits, 100MHz for pulse shape analysis & energy is normal But, don’t need PSA because detectors aren’t segmented and preamps are too slow. So 14 bits 50MHz would be fast enough. Real time processing up to 30kHz count rate (energy only) Data rate: 30k x (energy (2) + timestamp (6) + ID (2)) = 300kBytes/second per channel: 5Mbytes/sec/16 chan card. 100 channels = 30Mbytes/sec. From Ian Lazarus

16 Commercial electronics: why? Nicely packaged for our application Volume users (Radar, software radio)= sensible price Powerful FPGA built in Can process 50kHz singles rate on 48 channels 20-30Mbytes/sec output- OK over CPCI backplane Needs interface cards for TDR port and analogue matching From Ian Lazarus

17 TDR Interface ClkSync Rst out Err in Clk Ext trig gpio ADCs FPGA FPDPCPCI 16 Clk Ext trig gpio ADCs FPGA FPDPCPCI 16 Clk Ext trig gpio ADCs FPGA FPDPCPCI 16 Clk Ext trig gpio ADCs FPGA FPDPCPCI 16 CPCI host CPCI for setup, readout and control Diagram of example 64 channel DAQ system From Ian Lazarus

18 GREAT Metronome VHS-ADC TDR Port Clk 100 Sync Reset out Error in STFC- made TDR interface And clock fan-out Also Analogue Gain/offset Clock/TDR Interface card From Ian Lazarus

19 Clock/TDR Interface card From Ian Lazarus

20 Analogue Interface card From Ian Lazarus

21 Lyrtech digitiser cards purchased for another project have been evaluated. Electronics and DAQ work has confirm the suitability of new (commercial) digitisers, built by Lyrtech, as the basis for EDAQ in experiments such as SAGE and LISA.. Software for backplane data readout has already been implemented by V. Pucknell Summary

22 a NIM card has been designed and built to interface the new digitisers with the GREAT TDR and clock system. This card is being commissioned now (Spring 2007), and the VHDL code for its programmable logic has recently been completed. Another NIM card has been built and is being debugged which allows gain and offset control for the digitiser inputs (controlled over Ethernet link). Summary