SU-8 Testing (v1g) Thin SU8 on glass slide Test: (1)Soft Bake (SB) and (2)Post Exposure Bake (PEB) 1.

Slides:



Advertisements
Similar presentations
SU8 process Soft Bake (SB) for thin SU8
Advertisements

PMMA & HSQ trend chart December 2012 Sangeeth kallatt.
Electrical transport and charge detection in nanoscale phosphorus-in-silicon islands Fay Hudson, Andrew Ferguson, Victor Chan, Changyi Yang, David Jamieson,
Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.
Fabrication pH Electrode Using Lift-Off Method and Electrodeposition Presented by Na Zhang.
PDMS processing & devices. 2 nd master PDMS 1 st master PDMS control channel active channel PDMS 3 rd substrate.
Metamaterials Zaven Kalfayan Lindsay Hunting Phyllis Xu Joy Perkinson.
ECE/ChE 4752: Microelectronics Processing Laboratory
Lithography – Basic Concept
John D. Williams, Wanjun Wang Dept. of Mechanical Engineering Louisiana State University 2508 CEBA Baton Rouge, LA Producing Ultra High Aspect Ratio.
Creating Snow flake structures using EBL Date:January 2011 by:Lejmarc Snowball Principle Investigator:Dr. William Knowlton for:Nanoscale Materials and.
SU-8 Testing (v1f) Thin SU8 on glass slide Test: (1)Soft Bake (SB) and (2)Post Exposure Bake (PEB)
Prototype Showcase  What is a metamaterial?  How our 2-D sample was created  How our phase mask was created  SEM images of 2-D sample and phase mask.
Dielectric Properties of Ceramic Thin Films Mara Howell Materials Science and Engineering Junior, Purdue University Professor Kvam, Research Advisor.
299 Analysis For data: 299step.xlsx, 299.pxp. Summary of Nb (15nm)/Al 2 O 3 (15nm Pad;4-0nm wedge)/Co(30nm) 2.Try to etch Nb with CF 4 3.Nb etch.
Interference Applications Physics 202 Professor Lee Carkner Lecture 25.
Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory
Origin of Coulomb Blockade Oscillations in Single-Electron Transistors
Copyright © 2007, Pearson Education, Inc., Publishing as Pearson Addison-Wesley. Electric potential energy Electric potential Conservation of energy Chapter.
Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC
6. Interference by thin films t No phase shift (if n 2 < n 1 ) Phase shift -_____ (if n 2 > n 1 ) If there is a very thin film of material – a few wavelengths.
Zarelab Guide to Microfluidic Lithography Author: Eric Hall, 02/03/09.
ACTFEL Alternating Current Thin Film Electroluminescent Lamps.
Physics 6C Interference of EM Waves Prepared by Vince Zaccone For Campus Learning Assistance Services at UCSB.
Method of Level Measurement
Research Results Overview Review of former work on instantaneous fluid film thickness measurements Review of former work on instantaneous fluid film thickness.
Physics 4 Interference of EM Waves Prepared by Vince Zaccone For Campus Learning Assistance Services at UCSB.
Dynamic Presentation of Key Concepts Module 2 – Part 3 Meters Filename: DPKC_Mod02_Part03.ppt.
Practical Aspects of Logic Gates COE 202 Digital Logic Design Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum.
6. Interference by thin films
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
Lecture 4 Photolithography.
Charge collection studies on heavily diodes from RD50 multiplication run G. Kramberger, V. Cindro, I. Mandić, M. Mikuž Ϯ, M. Milovanović, M. Zavrtanik.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
1 © Unitec New Zealand DE4401 DC C APACITANCE AND CAPACITORS.
Regents Physics Circuits Unit Part I Resistivity and Ohm’s Law.
Dan Cheng 1/13/2015 LARP Copper Plated Trace Development Update.
Sally Seidel 1 3D Sensor Studies at New Mexico Sally Seidel for Martin Hoeferkamp, Igor Gorelov, Elena Vataga, and Jessica Metcalfe University of New Mexico.
1 SU-8 Testing (v1l) Thin SU8 on glass slide Test: Soft Bake (SB) and Post Exposure Bake (PEB)
EE 4345 Chapter 6 Derek Johnson Michael Hasni Rex Reeves Michael Custer.
Microelectronic Circuit Design McGraw-Hill Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock.
Asian Hair: greatest diameter with circular shape Caucasian and African hair: elliptical shape.
UNIVERSITY OF NOTRE DAME Origin of Coulomb Blockade Oscillations in Single-Electron Transistors Fabricated with Granulated Cr/Cr 2 O 3 Resistive Microstrips.
BioMEMS Device Fabrication Procedure Theresa Valentine 8/19/03.
Chapter 25 Capacitance.
Center for Materials for Information Technology an NSF Materials Science and Engineering Center Optical Lithography Lecture 13 G.J. Mankey
SU-8 is a polymer EPON SU-8
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
SU-8 Testing (v1b) Thin SU8 on glass slide Test Soft Bake (SB) and Post Exposure Bake (PEB)
The Fate of Silicon Technology: Silicon Transistors Maria Bucukovska Scott Crawford Everett Comfort.
SU-8 Testing (v1h) Thin SU8 on glass slide Test: (1)Soft Bake (SB) and (2)Post Exposure Bake (PEB) 1.
TECHNOLOGIES ESO 4 UNIT 1: ELECTRICITY AND ELECTRONICS ANALOGIC ELECTRONICS (PART 1)
The MicroBooNE Cryostat Wall as EMI Shield We estimate the noise charge induced on a TPC wire. We start with Marvin Johnson’s analysis of the transfer.
Wisconsin Center for Applied Microelectronics
EE 3311/7312 MOSFET Fabrication
Interference of EM Waves
Electron-beam lithography with the Raith EBPG
Electron-beam lithography with the Raith EBPG
6.3.3 Short Channel Effects When the channel length is small (less than 1m), high field effect must be considered. For Si, a better approximation of field-dependent.
Test Soft Bake (SB) and Post Exposure Bake (PEB)
MEMS 설계제작 Project Method of Wafer patterning.
Sitton Spelling Refresher
Electron-beam lithography with the Raith EBPG
BioMEMS Device Fabrication Procedure
7J Revision Quiz.
COMPONENTS.
LITHOGRAPHY Lithography is the process of imprinting a geometric pattern from a mask onto a thin layer of material called a resist which is a radiation.
Lecture #15 OUTLINE Diode analysis and applications continued
Photolithography.
Progress of DLC Resistive Electrode
Presentation transcript:

SU-8 Testing (v1g) Thin SU8 on glass slide Test: (1)Soft Bake (SB) and (2)Post Exposure Bake (PEB) 1

“Control” Recipe Spin Coating: rpm; rpm –expected thickness: 600 nm Soft Bake (SB): 60 93°C Exposure: W PEB: 93°C Develop: 4 min in SU8 developer SU8 developer rinse IPA rinse/Nitrogen Dry 2

1 st Set of Tests 4 samples; 8 devices/sample 4 Wells (W)+4 Blanks (B)/sample S1: “Control”: Misaligned (see next slide); All shorted; R(W) ~ 8.6 Ω; R(B) ~ 10 Ω Test Parameters for S2-4: –SB (RT Evap) and 60°C, same times for each S2: 8 min: R(W) = (2.7±0.8) Ω; R(B) = (11±0) MΩ; C(B) = (15.0 ± 0.1) pF S3: 13 min: Also misaligned (see next slide) R(W) = (4.9±?) Ω; R(B) = (6 ± 8) MΩ; C(B) = (17.0 ± 0.5) pF S4: 15 min: R(W) = (4 ± 1) Ω; R(B) = (11±0) MΩ; C(B) = (17 ± 0) pF Cracking patterns seen in S2, S3, S4 3

Findings/Discussion 1 st Set “Control”: All shorted –The “misalignment” ONLY causes 1.Top contacts don’t fully overlap guide circles on bottom that could result in the top contact not covering the well (is this the case? If not say so) – will NOT cause short 2.Top contacts touching two exposure regions –either single + double exposures (normal) – NOT cause short, –or single + no exposures (should not happen but may - according to Mark, but microscopy can tell us – presence of a well – check to confirm and revise here …) – MAY cause short (ONLY no exposure) RT Evap + 60°C at various times: All good –All Wells are shorted with a narrow range of R –All Blanks have good Cs also with narrow range Next thing to do is to estimate thickness from geometry from C –The two longer time ones exhibit ~10% larger C (difference in dielectric constants or thickness?) –All three show undesirable cracking patterns (under baked/sticky surface or over baked – low solvent, bubbling etc.?) 4

2 nd Set of Test Samples 4 samples 2 “Controls”: S5-6 Test Parameters for S7-8: –1 min 93°C and Vary SB 60°C S7: SB: 2.5 min S8: SB: 5 min 5

2 nd Test Results - “Control 1” S5 DeviceCapacitance( pF) Resistance( Ω) Type 129.4B 20.5W x10 6 B 424W 524B 67W 7 421B 817W Summary: W: 4/4 Shorted B: 3/4 Shorted R(W): (12 ± 10) Ω Excluding #3 R(B): (158± 230) Ω C(B,#3) – very low (9.38 pF) compared to 1 st set but comparable to S6 (also a Control - next slide). 6

“Control 2” S6 DeviceCapacitance( pF) Resistance( Ω) Type 1 Damaged9.74.6x10 6 W x10 6 B 3 Damaged x10 5 W x10 7 B 5142W x10 7 B 746W x10 4 B Summary: W: 2/4 Shorted (2 Damaged by high voltage – 1V) B: 0/4 Shorted R(W): (94± 68) Ω; C(B): (9.6± 0.5) pF 7

2.5 min SB S7 DeviceCapacitance( pF) Resistance( Ω) Type 113.4W 2428B 310.8W 4294B 53.7W 65.7B 74.1W 811.6B Summary: All Shorted R(B): (185 ± 211) Ω; R(W): (8 ± 5) Ω 8

5 min SB S8 DeviceCapacitance( pF) Resistance( Ω) Type 14.8W 216B 31.9W 444B 54.3W 6?B 7*15.16Very HighW x10 6 B Summary: W: 3/4 Shorted (why not 4/4?) B: 3/4 Shorted R(Blank): (30 ± 20) Ω (#8 excluded) R(Well): (3.7 ± 1.6) Ω (#7 excluded) 7*: Re-measured and consistent with capacitance 9

Findings/Discussion for 2 nd Set (S5-S8) The two “Controls”: –S5 is essentially all shorted, but R(B) > 10R(W) –S6 is nominally good aside from the 2 damaged devices. But, the 2 shorts are too resistive (~90 Ω) compared to the “benchmark” Set 1 (~few Ω). –C(B) are ~ 9.5 pF rather than pF for set 1 (thicker, lower dielectric constants, etc?) –The “Control” recipe is at best marginal thus unreliable (2 shorted and one nominally good out of 3 samples in sets 1 and 2) – consistent with prior Si wafer work (Matt) S7 and S8 are all shorted, but 20R(W) < R(B) and R(W)<10Ω, These are more consistent with Set 1 aside from being all shorted. The one good blank out of S8 has capacitance consistent with Set 1 capacitances (S2). 10

“Control 20x This image size is good (covering the entire crossbar) – perhaps larger ones covering up to the reference dots would be even better; at the current stage, there’s no need to have too many zoomed in images. 11

“Control 2” 100x 12

“Control1” 100x 13

2.5min SB 100x 14

5min SB 100x 15

3 rd Set of Test Samples 2 samples Test Parameters for S9-10: –1 min 93°C and Vary SB 60°C (longer SB compared to 2 nd set) S9: SB: 8 min S10: SB: 12 min 16

Back Contact not continuous – visually can’t see where it’s broken Measured Cs (can measure 2-terminal R) W: 2/4 Shorted B: 1/4 Shorted C(B): (19.3 ± 0.6) pF (excl. #2) DeviceCapacitance( pF) Resistance( Ω) Type 1W 2 B 312W 419B 5W 619B 7 W 820B 8 min - S9 17

12 min - S10 DeviceCapacitance( pF) Resistance( Ω) Type 14.5W 218B 36.7W 4121B 53.9W 6127B 75W 8 118B Summary: W: 4/4 Shorted B: 4/4 Shorted Avg Well Resistance: 5.0± 1.2Ω Avg Blank Resistance: 96± 52Ω Double Exposed (16s) 18

Discussion/Findings of Set 3 S9: –pretty much all open circuit –C(B) slightly higher than Set 1: 19 pF vs 15 and 17 pF –Current measurements unreliable because the back contact is not continuous without visual “flaws” S10: –All shorted –10R(W) < R(B) –Consistent with Set 2 19