Introduction to CAFE Yu Hen Hu & C. R. Kime Revised October 9, 2001.

Slides:



Advertisements
Similar presentations
Introduction to CAFE Yu Hen Hu September 25, 2000.
Advertisements

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part3: Verilog – Part 1.
Combinational Circuits ENEL 111. Common Combinationals Circuits NAND gates and Duality Adders Multiplexers.
ECE 301 – Digital Electronics Karnaugh Maps (Lecture #7) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,
ENGIN112 L8: Minimization with Karnaugh Maps September 19, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh.
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 6 Dr. Shi Dept. of Electrical and Computer Engineering.
CK Cheng Tuesday 10/2/02 CS 140 Lecture 2. Part I. Combinational Logic I) Specification –a. Language –b. Truth Table –c. Boolean Algebra –d. Incompletely.
Contemporary Logic Design Two-Level Logic © R.H. Katz Transparency No. 4-1 Chapter #2: Two-Level Combinational Logic Section 2.3, Switches and Tools.
Canonical Forms and Logic Miniminization
CS 151 Digital Systems Design Lecture 8 Minimization with Karnaugh Maps.
Introduction to Digital Logic Design Appendix A of CO&A Dr. Farag
Overview of Chapter 3 °K-maps: an alternate approach to representing Boolean functions °K-map representation can be used to minimize Boolean functions.
Lecture 4 Logic gates and truth tables Implementing logic functions
4.1 Conversion of English Sentences to Boolean Equations
طراحی مدارهای منطقی نیمسال دوم دانشگاه آزاد اسلامی واحد پرند.
©2004 Brooks/Cole FIGURES FOR CHAPTER 4 APPLICATIONS OF BOOLEAN ALGEBRA MINTERM AND MAXTERM EXPANSIONS Click the mouse to move to the next page. Use the.
1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC. K-Map (1)  Karnaugh Mapping is used to minimize the number of logic gates that are required in a digital circuit.
F = ∑m(1,4,5,6,7) F = A’B’C+ (AB’C’+AB’C) + (ABC’+ABC) Use X’ + X = 1.
Logic Gates Logic gates are electronic digital circuit perform logic functions. Commonly expected logic functions are already having the corresponding.
Basic Overview of VHDL Matthew Murach Slides Available at:
Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.
Boolean Algebra and Reduction Techniques
Functional Modeling.
THE K-MAP.
Introduction to Verilog. Data Types A wire specifies a combinational signal. – Think of it as an actual wire. A reg (register) holds a value. – A reg.
1 An algebraic structure consists of –a set of elements B –binary operators {+,.} –and a unary operator { ‘ } Such that following holds –Membership: B.
CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 4: Cost of Logic Circuits and Karnaugh Maps José Nelson Amaral.
COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.
Gates AND, OR, NOT NAND, NOR Combinational logic No memory A set of inputs uniquely and unambiguously specifies.
Logic Gates and Boolean Algebra Introduction to Logic II.
1 CS 352 Introduction to Logic Design Lecture 2 Ahmed Ezzat Boolean Algebra and Its Applications Ch-3 + Ch-4.
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC:K-Map. K-Map (1)  Karnaugh Map provides a systematic method for simplifying Boolean expressions and may produce.
UNIT 4 APPLICATIONS OF BOOLEAN ALGEBRA MINTERM AND MAXTERM EXPANSIONS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.
Discrete Systems I Lecture 09 Minterms and Decoders Profs. Koike and Yukita.
1 CSE370, Lecture 4 Lecture 4 u Logistics n HW1 due now n HW2 posted now and is due one week from today n Lab1 going on this week n Feedback on lectures,
Combinational Circuits and Boolean
Lecture 4 Logistics Last lecture --- Boolean algebra Today’s lecture
ECE 2110: Introduction to Digital Systems
Lecture 5 Topics Canonical or Standard Forms of Functions
ECE 3110: Introduction to Digital Systems
Plotting functions not in canonical form
Digital Logic.
CHAPTER 3 SETS AND BOOLEAN ALGEBRA
XOR, XNOR, and Binary Adders
CSE 311 Foundations of Computing I
Instructor: Alexander Stoytchev
Karnaugh Mapping Karnaugh Mapping Digital Electronics
CSE 370 – Winter Combinational Logic - 1
XOR, XNOR, & Binary Adders
ELL100: INTRODUCTION TO ELECTRICAL ENGG.
Karnaugh Mapping Digital Electronics
CSE 370 – Winter 2002 – Logic minimization - 1
ECE 331 – Digital System Design
Karnaugh Mapping Karnaugh Mapping Digital Electronics
Lecture 6 Logistics Last lecture Today’s lecture
Lecture 7 Logistics Last lecture Today HW2 due now Lab2 going on
Lecture 11: Hardware for Arithmetic
Karnaugh Mapping Digital Electronics
Karnaugh map Karnaugh map allows viewing the function in a picture form Map is arranged such that two neighbors differ in only one variable It is easy.
Lecture 4 Minterm and Maxterm
Lecture 4 Logistics Last lecture --- Boolean algebra Today’s lecture
Special Gates Combinational Logic Gates
Karnaugh Maps (K maps).
Analysis of Logic Circuits Example 1
Lecture 7 Logistics Last lecture Today HW2 due now Lab2 going on
XOR, XNOR, and Binary Adders
Dept of Electronics Engineering
COE 202 Introduction to Verilog
Presentation transcript:

Introduction to CAFE Yu Hen Hu & C. R. Kime Revised October 9, 2001

Introduction CAFE (Connection Arrays From Equations) is a Boolean function simplification program that can simultaneously simplify a set of Boolean functions sharing the same set of Boolean variables. To use CAFE, you create an input file which consists of –Function specifications: A list of functions to be minimized. Can be Boolean equations, a truth table, minterms, maxterms, or a tabular form –Process specification: specifies what kind of output you want

CAFE Syntax A sample CAFE program: Full Adder g=a*b, cout=g+p*cin. c s cout. Variables: case sensitive, but commands are case in- sensitive. Boolean operators: -, ~, / not *, & AND $, ~& XOR # A*~B !, ~| NOR +, | OR () punctuation, end of equation. end of last equation or other specification

Function Specifications : var_out = Boolean_expr = Boolean_expr. –If multiple outputs separated by, –Optional: dummy = all input variables ANDed together - used to order variables. : –Input var list. E.g. 3 a b cin. –var_out = minterm #s. : –Same as minterm : 3 a b c. x = 1x1 x10 = x00. Everywhere else, x = 0 : 4 a b c d. Inputs 3 w x y. Outputs 0 0 x – 0 x 1 x Note: x or X or - in inputs, means variable missing; in outputs, means don’t care. Terms for x = 1 Terms for x = don’t care Expr for var_out = 1 Expr for var_out = don’t care

Process Specifications and Commands Process specifications tells what format of the output should be. C: connection array E: equations T: truth table Advanced specifications: – K, L, R: not covered or used here. Terminal command for running CAFE: cafe [option] infile outfile Options:  -e Suppress echo of input equations with results  -f Fast connection arrays (the cheap solution of questionable quality)  -r Repeat reduction  -x Extraction algorithm (the systematic procedure we studied; may run long time!)

Example 1: Truth Table to Equations Input file: optran as at left 5 op2 op1 op0 sign corr.Command: cafe –x optran optran.out 2 sub comp_a X X X X X X X X 1 X 0 X X X 1 X X 0 X X 1 X X X 0 X X. e sub comp_a. q

Example 1: Truth Table to Equations CONTINUED: Connection Arrays from Equations Feb :00:09 Page 1 File: op_tran Run Options: x 1: 2: 5 op2 op1 op0 sign corr. 3: 2 sub comp_a. 4: : : X : X : X X X X : : : X X 1 X 0 X X 12: X 1 X X 0 X X 13: 1 X X X 0 X X 14: X 0 X : e sub comp_a. sub = -sign*-corr + -op0*-corr comp_a = corr + -op0*-corr seconds

Example 2: Minterms to Equations Connection Arrays from Equations Sep :08:59 Page 1 File: adder1 Run Options: 1: adder1 2: 3 a b cin. 3: s = , 4: co = : 6: e s co. s = -a*-b*cin + -a*b*-cin + a*-b*-cin + a*b*cin co = b*cin + a*cin + a*b

Example 3: Minterms to Truth Table 1: adder1 2: 3 a b cin. 3: s = , 4: co = : 6: t s co. 3 Input Variables 2 Output Variables 8 Cube Truth Table abc sc i o n Connection Arrays from Equations Sep :39:37 Page 1 File: adder1 Run Options: