Unit 9 Multiplexers, Decoders, and Programmable Logic Devices Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

22004/04/05Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

32004/04/05Fundamentals of Logic Design Programmable Logic Devices A general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions

42004/04/05Fundamentals of Logic Design Programmable Logic Arrays Performs the same basic function as a ROM n inputs and m outputs n inputs and m outputs m functions of n variables Differences in internal organization The decoder is replaced with an AND array The decoder is replaced with an AND array OR array OR array PLA : a sum-of-product expression ROM : truth table

52004/04/05Fundamentals of Logic Design PLA Structure

62004/04/05Fundamentals of Logic Design PLA with Three Inputs, Five Product Terms, and Four Outputs

72004/04/05Fundamentals of Logic Design AND-OR Array

82004/04/05Fundamentals of Logic Design PLA Table

92004/04/05Fundamentals of Logic Design PLA Realization f 1 = a’bd + abd + ab’c’ + b’c f 2 = c + a’bd f 3 = bc + ab’c’ + abd

102004/04/05Fundamentals of Logic Design PLA Structure

112004/04/05Fundamentals of Logic Design PLA Table v.s. Truth Table PLA Table Each row represents a general product term. Each row represents a general product term. 0, 1, or more rows may be selected. 0, 1, or more rows may be selected. ROM Truth Table Each row represents a minterm. Each row represents a minterm. Exactly one row will be selected. Exactly one row will be selected.

122004/04/05Fundamentals of Logic Design PLAs Mask-programmable PLAs Programmed at the time of manufacture Programmed at the time of manufacture Similar to mask-programmable ROM Similar to mask-programmable ROM Field-programmable PLAs (FPLAs) Use electronic charges to store a pattern in the AND and OR arrays Use electronic charges to store a pattern in the AND and OR arrays An FPLA with 16 inputs, 48 product terms and 8 outputs An FPLA with 16 inputs, 48 product terms and 8 outputs 8 functions of 16 variables Total number of product terms does not exceed 48

132004/04/05Fundamentals of Logic Design Programmable Array Logic PAL a special case of PLA a special case of PLA AND array is programmable OR array is fixed Less expensive Less expensive Easier to program Easier to program

142004/04/05Fundamentals of Logic Design PAL A buffer is used To drive many AND gate inputs To drive many AND gate inputs

152004/04/05Fundamentals of Logic Design PAL Connections to the AND gate inputs are represented by X’s

162004/04/05Fundamentals of Logic Design PAL segment

172004/04/05Fundamentals of Logic Design Full Adder The logic equations for the full adder are Sum = X’Y’C in + X’YC’ in + XY’C’ in + XYC in Sum = X’Y’C in + X’YC’ in + XY’C’ in + XYC in C out = XC in + YC in + XY C out = XC in + YC in + XY

182004/04/05Fundamentals of Logic Design Full Adder

192004/04/05Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

202004/04/05Fundamentals of Logic Design CPLDs As integrated circuit technology continues to improve, more and more gates can be placed on a single chip. Complex Programmable Logic Devices (CPLDs) Complex Programmable Logic Devices (CPLDs) When storage elements such as flip-flops are also included on the same IC, a small digital system can be implemented with a single CPLD.

212004/04/05Fundamentals of Logic Design Contents 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays

222004/04/05Fundamentals of Logic Design Field Programmable Gate Arrays FPGA An IC contains an array of identical logic cells with programmable interconnections An IC contains an array of identical logic cells with programmable interconnections The user can program Functions realized by each logic cell Functions realized by each logic cell Connections between the cells Connections between the cells

232004/04/05Fundamentals of Logic Design FPGA

242004/04/05Fundamentals of Logic Design Configurable Logic Block CLB Two function generators Two function generators Four inputs Can implement any function of up to four variables Implemented as lookup tables (LUTs) Two flip-flops Two flip-flops Various multiplexers for routing signals within the CLB Various multiplexers for routing signals within the CLB

252004/04/05Fundamentals of Logic Design Simplified CLB

262004/04/05Fundamentals of Logic Design Implementation of a LUT

272004/04/05Fundamentals of Logic Design Decomposition of Switching Functions To implement a switching function of more than four variables using 4-variable function generator The function must be decomposed into subfunctions The function must be decomposed into subfunctions Each subfunction requires only four variables Each subfunction requires only four variables

282004/04/05Fundamentals of Logic Design Shannon’s Expansion Theorem Expand a function of the variables a,b,c, and d about the variable a : f(a,b,c,d) = a’ f(0,b,c,d) + a f(1,b,c,d) f(a,b,c,d) = a’ f(0,b,c,d) + a f(1,b,c,d) = a’ f 0 + a f 1 = a’ f 0 + a f 1 f 0 = f(0,b,c,d): replace a with 0 in f(a,b,c,d) f 0 = f(0,b,c,d): replace a with 0 in f(a,b,c,d) f 1 = f(1,b,c,d): replace a with 1 in f(a,b,c,d) f 1 = f(1,b,c,d): replace a with 1 in f(a,b,c,d)

292004/04/05Fundamentals of Logic Design Expansion Example f(a,b,c,d) = c’d’ + a’b’c + bcd + ac’ = a’ (c’d’ + b’c + bcd) + a (c’d’ + bcd + c’) = a’ (c’d’ + b’c + cd) + a (c’ + bd) = a’ f 0 + a f 1

302004/04/05Fundamentals of Logic Design Expansion Example

312004/04/05Fundamentals of Logic Design Shannon’s Expansion Theorem General form : expanding an n-variable function about the variables x i : f(x 1, x 2,…, x i-1, x i, x i+1,…, x n ) f(x 1, x 2,…, x i-1, x i, x i+1,…, x n ) = x i ’ f(x 1, x 2,…, x i-1, 0, x i+1,…, x n ) + x i f(x 1, x 2,…, x i-1, 1, x i+1,…, x n ) = x i ’ f(x 1, x 2,…, x i-1, 0, x i+1,…, x n ) + x i f(x 1, x 2,…, x i-1, 1, x i+1,…, x n ) = x i ’ f 0 + x i f 1 = x i ’ f 0 + x i f 1

322004/04/05Fundamentals of Logic Design 5-variable function f(a, b, c, d, e) = a’ f(0, b, c, d, e) + a f(1, b, c, d, e) = a’ f 0 + a f 1 Any 5-variable function can be realized using two 4-variable function generators and a 2-to-1 MUX.

332004/04/05Fundamentals of Logic Design 5- and 6-variable functions

342004/04/05Fundamentals of Logic Design Supplement SIP Single In-line Package Single In-line PackageDIP Dual In-line Package Dual In-line PackagePGA Pin Grid Array Pin Grid ArraySIMM Single In-line Memory Module Single In-line Memory ModuleDIMM Dual In-line Memory Module Dual In-line Memory Module

352004/04/05Fundamentals of Logic Design Supplement IEEE Standard 1164 defines a std_logic type that has nine values: U : Uninitialized U : Uninitialized X : Unknown X : Unknown 0 : Logic 0 (driven) 0 : Logic 0 (driven) 1 : Logic 1 (driven) 1 : Logic 1 (driven) Z : High impedance Z : High impedance W : Weak 1 L : Logic 0 (read) H : Logic 1 (read) - : Don’t care

362004/04/05Fundamentals of Logic Design Homework # Paper Submission, due on April 8, Late submission will not be accepted.