MODERN 1 st Year Review ENIAC MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4 WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: June 22, 2010 ( hrs) Review period: :

CONFIDENTIAL 2 MODERN 1st Year Review June 22, 2010 Agenda General information (JvG) –Objectives –Consortium –Resources planned and used –Overview of deliverables and milestones status –Cooperation, dissemination and exploitation –Project management: progress, funding problems and amendments –Other issues, Q&A For WP1 (GG), WP2 (AJ), WP3 (WH), WP4 (DP) and WP5 (LV) –Relationship between workpackages –Progress, highlights and lowlights –Technical status and achievements of deliverables (incl. changes) –Cooperation –Dissemination (publications, patents), exploitation –Other issues, Q&A

CONFIDENTIAL 3 MODERN 1st Year Review June 22, 2010 Objectives The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are:  Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures.  Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI. oTiming, power and yield.  Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.  Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys)

CONFIDENTIAL 4 MODERN 1st Year Review June 22, 2010 Consortium The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. 9 Countries28 Partners

CONFIDENTIAL 5 MODERN 1st Year Review June 22, 2010 Resources planned and used

CONFIDENTIAL 6 MODERN 1st Year Review June 22, 2010 Overview of deliverables and milestones status (1)

CONFIDENTIAL 7 MODERN 1st Year Review June 22, 2010 Overview of deliverables and milestones status (2)

CONFIDENTIAL 8 MODERN 1st Year Review June 22, 2010 Overview of deliverables and milestones status (3)

CONFIDENTIAL 9 MODERN 1st Year Review June 22, 2010 Cooperation, dissemination and exploitation

CONFIDENTIAL 10 MODERN 1st Year Review June 22, 2010 Project management: progress, funding problems and amendments

CONFIDENTIAL 11 MODERN 1st Year Review June 22, 2010 Other issues Q&A

CONFIDENTIAL 12 MODERN 1st Year Review June 22, 2010 WP1: Relationship between workpackages

CONFIDENTIAL 13 MODERN 1st Year Review June 22, 2010 WP1: Progress, highlights and lowlights Task T1.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions.

CONFIDENTIAL 14 MODERN 1st Year Review June 22, 2010 WP1: Technical status and achievements of deliverables (incl. changes)

CONFIDENTIAL 15 MODERN 1st Year Review June 22, 2010 WP1: Cooperation WP leader: ST-I If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

CONFIDENTIAL 16 MODERN 1st Year Review June 22, 2010 WP1: Dissemination (publications, patents), exploitation

CONFIDENTIAL 17 MODERN 1st Year Review June 22, 2010 WP1: Other issues, Q&A

CONFIDENTIAL 18 MODERN 1st Year Review June 22, 2010 WP2: Relationship between workpackages

CONFIDENTIAL 19 MODERN 1st Year Review June 22, 2010 Task T2.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. WP2: Progress, high- and lowlights

CONFIDENTIAL 20 MODERN 1st Year Review June 22, 2010 WP2: Technical status and achievements of deliverables (incl. changes)

CONFIDENTIAL 21 MODERN 1st Year Review June 22, 2010 WP2: Cooperation WP leader: STF2 If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

CONFIDENTIAL 22 MODERN 1st Year Review June 22, 2010 WP2: Dissemination (publications, patents), exploitation

CONFIDENTIAL 23 MODERN 1st Year Review June 22, 2010 WP2: Other issues, Q&A

CONFIDENTIAL 24 MODERN 1st Year Review June 22, 2010 WP3: Relationship between workpackages

CONFIDENTIAL 25 MODERN 1st Year Review June 22, 2010 WP3: Physical/circuit to RT-level Objective –PV-aware and PV-robust circuit design techniques and tools, enabling the design of reliable, low cost, low power, low EMI digital and AMS&RF products Tasks: 1.PV-aware circuit models 2.Methodologies, tools and flows for manufacturability, testability, reliability and yield 3.PV-aware design 4.Design for low noise and EMI/EMC Progress: –The activity is on track, and planned deliverables were delivered –milestones are on track –A number of scientific papers were published in 2009

CONFIDENTIAL 26 MODERN 1st Year Review June 22, 2010 Task T3.1: PV-aware circuit models Partners: TUD, LIRM, NXP, ST-I, TUE, UNRM Process variation will be included in existing physical and symbolic circuit models. These models are essential to effectively predict delay variations in order to be able to design reliable and predictable electronic circuits. D3.1.1NXP, ST-I, TUD, TUE, UNRM: Set of alternative symbolic models for lib cells Highlights –statistical standard cell model based upon statistical transistor models –algorithms to create a transistor-level simulator –Statistical analysis resulted in: there are four different groups of paths from STA vs SPICE analysis a novel statistical method has been developed for outlier identification, a linear mixed model has been developed by taking the random and fixed effects into account for predicting the delay of a path. –Build of VHDL delay models for standard cells which depend on technology parameters, allowing Monte Carlo analysis of variability in delay already at the logic level –Verilog-A models which account also for process, design and operation parameters WP3: Progress, high- and lowlights

CONFIDENTIAL 27 MODERN 1st Year Review June 22, 2010 T3.1 TUD&TUE&NXP: TL Statistical Standard Cell Models for STA

CONFIDENTIAL 28 MODERN 1st Year Review June 22, 2010 T3.1 TUD&TUE&NXP: TL Statistical Standard Cell Models for STA

CONFIDENTIAL 29 MODERN 1st Year Review June 22, 2010 T3.1 UNRM: VHDL Cell delay models

CONFIDENTIAL 30 MODERN 1st Year Review June 22, 2010 T3.1 STI: Analogue Circuit Models

CONFIDENTIAL 31 MODERN 1st Year Review June 22, 2010 Task T3.2: Methodologies, tools and flows for manufacturability, testability, reliability and yield Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM To compensate for process variation during circuit design the PV-aware circuit models need to be used in new methods for circuit design and future design tools and flows D3.2.1 ST-I, UNBO, UNCA, UNRM: Circuit techniques, and speed-up algorithms for PV-aware circuit simulation Highlights: –Adaptive Body Bias technique has been implemented –First results of an optimization procedure for circuit design –Influence of random process variations on speed and energy consumption has been analyzed Change of focus: circuit design techniques rather than simulation speed-up techniques WP3: Progress, high- and lowlights

CONFIDENTIAL 32 MODERN 1st Year Review June 22, 2010 T3.2 UNBO: Adaptive Body Bias techniques

CONFIDENTIAL 33 MODERN 1st Year Review June 22, 2010 T3.2 UNCA: Influence of random process variations on speed and energy consumption Flip-Flops circuits: (a) TGMS; (b) MC2MOS; (c) SAFF; (d) HLFF; (e) SDFF

CONFIDENTIAL 34 MODERN 1st Year Review June 22, 2010 T3.2 UNRM STI: optimization procedure for circuit design First results on on optimization procedure obtained Performance index can be reduced to of first attempt Learning machines defined: –Artificial Neural Networks –Support Vector Machines

CONFIDENTIAL 35 MODERN 1st Year Review June 22, 2010 Task T3.3: PV-aware design Partners (underlined task leader) : POLI, CSEM, IFXA, LETI, NXP, UPC Solutions for PV-aware circuit design are proposed by either a monitor & control strategy or by development of low PV sensitive standard cell libraries. Inherently variability robust designs are introduced by restricted design rules, redundant/spare transistors and self-timed logic. D3.3.1 CSEM, IFXA, LETI, NXP, POLI, UPC: PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF Highlights: –new methodologies for the assessment of reliability, including PV and aging –monitor and control strategies on AMS&RF circuits –M&C strategies proposing new PVT monitors –automated monitor insertion methodology –sleep transistors used for power-gating –design strategies for PV tolerant circuits WP3: Progress, high- and lowlights

CONFIDENTIAL 36 MODERN 1st Year Review June 22, 2010 T3.3 IFX: monitor & control strategies on AMS&RF

CONFIDENTIAL 37 MODERN 1st Year Review June 22, 2010 T3.3 LETI: PV aware solutions for digital W1 ratioW2 ratio Temp/Power0,911,11,20,911,11, ,29102,4099,6198,7091,9091,2790,9290, ,8796,0194,1693,3590,1789,4889,3589, ,1292,3489,6288,6189,0688,1087,9287, ,4593,1191,6190,3388,6587,6387,3887,24

CONFIDENTIAL 38 MODERN 1st Year Review June 22, 2010 T3.3 POLI: PV effects in Power-Managed Circuits benchfnomfwcftuned b b b b b b b b Δ 0%-27%+2%

CONFIDENTIAL 39 MODERN 1st Year Review June 22, 2010 T3.3 CSEM&UPC: PV tolerant circuits The work done by CSEM : –Source biasing –Standard Cell Library using a few cells to provide a better compensation of PV effects –Standard Cell Library using regular layout or restricted design rules, with or without redundancy –Probabilistic CMOS (PCMOS) taking into account that each gate has a probability of failure. –Approximate arithmetic The work of UPC has involved the following topics: –Regular configurable cell (VCTA) design –Probabilistic evaluation of digital circuits –Approach to digital logic tolerant to noise

CONFIDENTIAL 40 MODERN 1st Year Review June 22, 2010 Task T3.4: Design for low noise and EMI/EMC Partners : NXP, LIRM, ST-I Next to process variation there is also a large contribution to the timing variation from EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of AMS&RF the analogue circuits risks suffering from the digital noise. New design techniques will be proposed to suppress and canalise noise and EMI for improved reliability of the complete electrical system. D3.4.1 LIRM, ST-IM: Impact of supply noise, and clock distribution on EMI and circuit timing D3.4.2 NXP: RF-interaction models for combined PCB-package-IC Highlights –Significant attenuation in EM conducted emissions by decoupling insertion & optimization –Successful tape-out following methodology –flow allowing simulating the time domain evolutions of the magnetic emissions –validated by comparing the predicted emissions of two ICs –RF interaction models improved by: Parasitic extraction, De-embedding techniques, package modelling WP3: Progress, high- and lowlights

CONFIDENTIAL 41 MODERN 1st Year Review June 22, 2010 T3.4 STI&LIRM: magnetic field simulation flow Measurement Simulation

CONFIDENTIAL 42 MODERN 1st Year Review June 22, 2010 T3.4 NXP: RF interaction models PCB-package-IC

CONFIDENTIAL 43 MODERN 1st Year Review June 22, 2010 WP3: Technical status and achievements of deliverables (incl. changes)

CONFIDENTIAL 44 MODERN 1st Year Review June 22, 2010 WP3: Cooperation WP leader: NXP Collaborations –NXP, TUD, TUE NXP delivers path delay measurement data, TUE STA timing correlation TUD delivers models at transistor level Regular face-to-face meetings and conference calls –UNIRM UNBO STI TUD Regular and material exchange STI and UNRM face 2 face an almost weekly phone contact UNBO has strong collaboration with STI –POLI, LETI Poli relies on Leti to receive tools for var. assessment –CSEM, UPC, LETI, LIRM Discussions on tolerant circuits and regular layouts LETI and LIRM have strong collaboration on M&C, regualr phone calls UPC has contac with LETI and CSEM on temp. mon. and regular layouts –NXP LIRM ST Conference calls

CONFIDENTIAL 45 MODERN 1st Year Review June 22, 2010 WP3: Dissemination (publications, patents), exploitation Accepted: –Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "A Simplified Transistor Model for CMOS Timing Analysis", Proceedings of ProRISC 2009 –Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis", Proceedings of DAC –Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Statistical Moment Estimation in Circuit Simulation", Proceedings of VARI 2010 –Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Transistor Level Waveform Evaluation for Timing Analysis", Proceedings of VARI –P. Joubert Doriol, C. Forzan, D. Villa, D. Pandini, R. Castellan, D. Cervini, M. Rotigni, G. Graziosi, G. Contarino, and E. Marzorati, “Power Rail Noise Minimization for EMC-aware Design,” in Proc. SNUG, Mar –P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi, and D. Pandini, “EMC-aware Design on a Microcontroller for Automotive Applications,” in Proc. DATE, Apr –G. Graziosi, P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, and D. Pandini, “Advanced Modeling Techniques for System- level Power Integrity and EMC Analysis,” in Proc. EMPC, Jun – C. Forzan and D. Pandini, “Statistical Static Timing Analysis: A Survey,” Integration, the VLSI Journal, vol. 42, pp , Jun – P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi, and D. Pandini, “Electromagnetic Interference Reduction on an Automotive Microcontroller,” in Proc. Design Automation Conf., Jul Submitted: –Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations", submitted to PATMOS 2010 –Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, "Noise Analysis of Non-Linear Dynamic Integrated Circuits", submitted to CICC 2010 pdf –Amir Zjajo, Qin Tang, Jose Pineda de Gyvez, Michel Berkelaar, Alessandro Di Bucchianico, Nick van der Meijs, "Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs", submitted to IEEE Transactions on Circuits and Systems-I: Regular Papers. –Amir Zjajo, Manuel Barragan, Jose Pineda de Gyvez, "Process Variation Monitoring Enhanced Calibration and Debugging of Multi-Step Analog to Digital Converters", submitted to IEEE Transactions on Circuits and Systems-I: Regular Papers.

CONFIDENTIAL 46 MODERN 1st Year Review June 22, 2010 WP3: Other issues, Q&A

CONFIDENTIAL 47 MODERN 1st Year Review June 22, 2010 WP4: Relationship between workpackages

CONFIDENTIAL 48 MODERN 1st Year Review June 22, 2010 Task T4.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. WP4: Progress, high- and lowlights

CONFIDENTIAL 49 MODERN 1st Year Review June 22, 2010 WP4: Technical status and achievements of deliverables (incl. changes)

CONFIDENTIAL 50 MODERN 1st Year Review June 22, 2010 WP4: Cooperation WP leader: ST-I If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

CONFIDENTIAL 51 MODERN 1st Year Review June 22, 2010 WP4: Dissemination (publications, patents), exploitation

CONFIDENTIAL 52 MODERN 1st Year Review June 22, 2010 WP4: Other issues, Q&A

CONFIDENTIAL 53 MODERN 1st Year Review June 22, 2010 WP5: Relationship between workpackages

CONFIDENTIAL 54 MODERN 1st Year Review June 22, 2010 Task T5.x: Task name Partners (underlined task leader) : Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. WP5: Progress, high- and lowlights

CONFIDENTIAL 55 MODERN 1st Year Review June 22, 2010 WP5: Technical status and achievements of deliverables (incl. changes)

CONFIDENTIAL 56 MODERN 1st Year Review June 22, 2010 WP5: Cooperation WP leader: NMX If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when)

CONFIDENTIAL 57 MODERN 1st Year Review June 22, 2010 WP5: Dissemination (publications, patents), exploitation

CONFIDENTIAL 58 MODERN 1st Year Review June 22, 2010 WP5: Other issues, Q&A

CONFIDENTIAL 59 MODERN 1st Year Review June 22, 2010