Micron Technology Clinic Effect of Transistor Number and Hierarchy on Simulation Speed Presented by: Jason Oneida Advisor: Dr. Ken Stevens.

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Micron Technology Clinic Effect of Transistor Number and Hierarchy on Simulation Speed Presented by: Jason Oneida Advisor: Dr. Ken Stevens

Overview ► Advantages of Two-Phase Analysis?  Simulation speed  Accurate abstraction  Hierarchy in simulation ► Experiment: Cascading multipliers  Test importance of hierarchy in design  Scaling hierarchical mesh of 16-bit multipliers  Implementation notes: Galois LFSR ► Data comparison  HSimPlus and HSPICE  Conclusions regarding Two-Phase Analysis

Experimental Setup ► Hypothesis: Hierarchy in execution will result in faster run-time  Two-Phase Analysis and hierarchy  Micron single-layer package model ► Metric for comparison  Number of transistors vs. simulation time [1] “Central Processing Unit,” schools-wikipedia.org, Jan – Jan [Online]. Available: wikipedia.org/wp/c/Central_processing_unit.htm[Accessed: March 29, 2010] wikipedia.org/wp/c/Central_processing_unit.htm

Circuit Design ► Cascaded multipliers  Hierarchy: divergent data path  Non-ideal modeling ► Pseudo-random input  Linear feedback shift register (LFSR)‏ ► Galois LFSR [2] “Linear Feedback Shift Register,” absoluteastronomy.com, Jan, [Online]. Available: [Accessed: March 29, 2010]

Multiplier Block Diagram

HSimPlus Results ► Plot features  Variables  Scale ► Data Points  Eight total ► Curve Fit  Initial region  Linear Portion

HSPICE Results ► Axes  Units ► Simulation time  10,000 sec. per every 100,000 transistors ► Curve Shape  Slope  Fit trend

Combined Results ► Data point discrepancy – 8 vs. 6 ► Speed difference

Sample Multiplier Output ► HSimPlus settings ► Values: approximately 5% error

Conclusions ► Experiment to show benefit of hierarchy on run-time using two phase models ► Validated with a scalable design  Hierarchical grids of multipliers  Pseudo-random number generators for data ► Hypothesis confirmed  HSimPlus scaled at about 1,000 sec. per 100,000 transistors  HSPICE scaled at about 10,000 sec per 100,000 transistors  Output accuracy within 5%