Figure A flip-flop with an enable input. D Q Q Q R Clock E 0 1

Figure Code for a D flip-flop with enable. module rege (R, Clock, Resetn, E, Q); input R, Clock, Resetn, E; output Q; reg Q; Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule

Figure An n-bit register with an enable input. module regne (R, Clock, Resetn, E, Q); parameter n = 8; input [n-1:0] R; input Clock, Resetn, E; output [n-1:0] Q; reg [n-1:0] Q; Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule

Figure A shift register with parallel-load and enable control inputs.

Figure A right-to-left shift register with an enable input. module shiftlne (R, L, E, w, Clock, Q); parameter n = 4; input [n-1:0] R; input L, E, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; Clock) begin if (L) Q <= R; else if (E) begin Q[0] <= w; for (k = 1; k < n; k = k+1) Q[k] <= Q[k-1]; end endmodule

Figure An SRAM cell. Sel Data

Figure A 2 x 2 array of SRAM cells. Sel 1 0 Data 0 1

Figure A 2 m x n SRAM block. Sel m 1” Read Write d 0 d n1– d n2– q 0 q n1– q n2– m -to-2 m decoder Address a 0 a 1 a m1– Data outputs Data inputs

Figure Pseudo-code for the bit counter. B=0; while A  0 do if a 0 =1 then B=B+1 ; end if; Right-shift A ; end while;

Figure ASM chart for the pseudo-code in Figure Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Datapath for the ASM chart in Figure

Figure ASM chart for the bit counter datapath circuit.

Figure Verilog code for the bit-counting circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Simulation results for the bit-counting circuit.

Figure An algorithm for multiplication. (a)Manualmethod P=0 ; for i=0 to n1 do if b i =1 then P=P+A ; endif; Left-shift A ; endfor; (b)Pseudo-code Multiplicand1 1 Product Multiplier  Binary  Decimal –

Figure ASM chart for the multiplier. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Datapath circuit for the multiplier. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure ASM chart for the multiplier control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Verilog code for the multiplier circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Simulation results for the multiplier circuit.

Figure An algorithm for division. R=0 ; for i=0 to n1 do Left-shift R  A ; ifR  B then q i =1 ; R=RB ; else q i =0 ; endif; endfor; (c) Pseudo-code Q A B R (a) An example using decimal numbers (b) Using binary numbers – –

Figure ASM chart for the divider. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Datapath circuit for the divider.

Figure ASM chart for the divider control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure An example of division using n = 8 clock cycles. Load A, B Clock cycle A/Q rr 0 R AB Shift left Subtract, Q 0 1  Shift left, Q 0 0 , Q 0 0 , Q 0 0  Subtract, Q 0 1 , Q 0 1 , Q 0 1  Shift left, Q 0 0 

Figure ASM chart for the enhanced divider control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Datapath circuit for the enhanced divider. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Verilog code for the divider circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Simulation results for the divider circuit.

Figure An algorithm for finding the mean of k numbers. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Datapath circuit for the mean operation. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure ASM chart for the mean operation control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Schematic of the mean circuit with an SRAM block.

Figure Simulation results for the mean circuit using SRAM.

Figure Pseudo-code for the sort operation. for i=0 to k2 do A=R i ; for j=i+1 to k1 do B=R j ; if B<A then R i =B ; R j =A ; A=R i ; end if; end for; – –

Figure ASM chart for the sort operation. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure A part of the datapath circuit for the sort operation.

Figure A part of the datapath circuit for the sort operation.

Figure ASM chart for the control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Verilog code for the sorting circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Simulation results for the sort operation. Please see “portrait orientation” PowerPoint file for Chapter 10

Figure Using tri-state buffers in the datapath circuit.

Figure Clock enable circuit. D Q Q Data Clock E

Figure An H tree clock distribution network. Clock ff

Figure A flip-flop in an integrated circuit.

Figure Flip-flop timing in a chip.

Figure Asynchronous inputs. D Q Q Data Clock (asynchronous) D Q Q Data (synchronous)

Figure Switch debouncing circuit. Data S R V DD R V R (a) Single-pole single-throw switch Data V DD R (b) Single-pole double-throw switch with a basic SR latch

Figure P10.1. Pseudo-code for integer division. Q=0 ; R=A ; while ((RB)>0) do R=RB ; Q=Q +1 ; end while; – –

Figure P10.2. The 555 programmable timer chip. 5 V R b R a 555 Timer C  F Clock (output)