D. GordonFIELDS iCDR – DCB Solar Probe Plus FIELDS Instrument CDR DCB Dorothy Gordon Space Sciences Lab, UC Berkeley 1

D. GordonFIELDS iCDR – DCB Agenda 2 o Requirements, ICDs, and Specifications o Block Diagrams o Development &Test o Power / Mass / Parts o Status / Next Steps

D. GordonFIELDS iCDR – DCB DCB Controlling Documents & Specification 3 Spacecraft Interface –Solar Probe Plus (SPP) General Instrument to Spacecraft Interface Control Document (ICD), Rev. A, 8/1/14, APL Drawing # –Solar Probe Plus (SPP) FIELDS to Spacecraft Interface Control Document (ICD), Rev. A, 10/7/14, APL Drawing # FIELDs Internal ICDs –SPF_MEP_100_CDI_ICD - Command/Data (CDI) Interface Control Document, Rev. 6 –SPF_MEP_101_TDS_ICD - Time Domain Sampler Interface Control Document, Rev. 3 –SPF_MEP_102_DFB_ICD - Digital Fields Board Control Document, Rev. 4 –SPF_MEP_103_MAG_ICD - MAG Electronics Boards Interface Control Document, Rev. 4 –SPF_MEP_104_AEB_ICD - AEB Interface Control Document, Rev. 4 –SPF_MEP_110_Connectors - SPF MEP Connectors and Pinouts, Rev. S DCB Design Document –SPF_DCB_001_Specification, Rev A Data Controller Board and FPGA Description and “User Manual” Schematics –SPF_ETU2_DCBSCH_REV 7 –FPGA Daughter Board (ProASIC FLASH FPGA) –RTAX Daughter Board (FLIGHT FPGA)

D. GordonFIELDS iCDR – DCB DCB/RFS as component of MEP 4

D. GordonFIELDS iCDR – DCB DCB/RFS Top Level Schematic 5

D. GordonFIELDS iCDR – DCB DCB/RFS ETU#2 Layout 6 RFS ADCs and Data Buffers RFS Frontend Analog Instrument & LNPS I/Fs RFS Memory (SRAM) (under FPGA DB) S/C I/F CPU Memory: SRAM, EEPROM & PROM FLASH Housekeeping Power Red = Top Side Components Blue = Bottom Side Components

D. GordonFIELDS iCDR – DCB DCB/RFS ETU#2 7 Six Signal Layers, 2 Power Layers, 2 Ground Layer RFS ground isolated from AGND and GND (general DCB ground) Resistor tie points provided for frame (chassis ground) connections ETU2 has been in test for approximately two months Processor, Memory (SRAM, EEPROM, FLASH) have been verified Housekeeping and Instrument Interfaces tested/integrated with FSW Verified operation of ADC Burst into RFS memory, time series data acquisition and transfer, spectra generation

D. GordonFIELDS iCDR – DCB Changes Since PDR 8 Design Evolution since PDR 8 Housekeeping channels added (total = 16) Protection added for external housekeeping inputs (LNPS and AEB) LF Mode average set at 8 (previously 10 ) On-board Power Supply detail design/test complete (includes LVDS fault mitigation) RFS Subsystem detailed design/build complete Design Test/Developments ETU1 used as initial test-bed Daughter boards designed and built ProASIC version (ProASIC pin ball grid array) In use prior to PDR, continues to be used for DCB and TDS ETUs Flight version (RTAX pin column grid array) layout, fabrication and population with APL team First version built for DFB, uses RTAX-Proto, tested at LASP with preliminary DFB FPGA fuse file) ETU1 used as initial test-bed ETU2 in operation since October, 2014

D. GordonFIELDS iCDR – DCB Testing with DCB/RFS ETU2 9 DCB/RFS testing with AEB and Preamp Integration with MEP (FIELDS1) Testing with MEP DCB/RFS powered by LNPS and integrated with AEB Signal input via preamp ETU2 integrates CPU, RFS ADCs and RFS frontend RFS Frontend standalone integration: standalone performance verified MEP (FIELDS1): Integration with LNPS, AEB, preamps

D. GordonFIELDS iCDR – DCB Power and Mass 10 DCB Flight Board Estimate: 1.8W Nominal 2.5W Worst-case (Maximum duty cycle over temperature) Power Allocation: 1.86W. Nominal Mass Allocation (RFS + DCB): 595 g. (without frame and EMI shield) Additions: RTAX Daughter board (CCGA heavier than plastic BGA) RFS “dog-house”

D. GordonFIELDS iCDR – DCB Parts (both DCB and RFS circuitry) 11 All components meet the TID Radiation Requirement All components are latchup immune Most components have been unconditionally approved by the APL Parts Board. 8 parts conditionally approved pending SEU analyses. TID Requirement >= 20krad

D. GordonFIELDS iCDR – DCB Status and Next Steps 12 Status DCB/RFS ETU2 – electrical subsystems 100% tested Minor changes for transition to Flight Layout FIELDS DCB Pre-iCDR Peer Review - Nov 20, RFAs; 12 Comments/Advisories FIELDS1 Integration Instrument and Spacecraft Interfaces operating successfully with FSW Upcoming Tasks Support integration of FIELDS1 subsystems & FSW, characterization of RFS Integration of FIELDS1/FIELDS2 Support MEP ETU Thermal-Vacuum Testing Migration to flight schematics/layout Parts Stress Analysis

D. GordonFIELDS iCDR – DCB Backup Slides 13

D. GordonFIELDS iCDR – DCB Requirements (1) 14

D. GordonFIELDS iCDR – DCB Requirements (2) 15 Baseline Instrument Requirements Document SPF_SYS_010_Instrument_Requirements_IRD CDRL# SE B

D. GordonFIELDS iCDR – DCB FIELDS DCB Pre-iCDR Peer Review Comments 16

D. GordonFIELDS iCDR – DCB FLASH MEMORY 3DFN64G08VS8305 – Samsung (8Gb Flash K9F8G08U0M) die packaged by 3D-Plus Total dose (TID) >= 60Krad(Si) Testing by Nam Kha (APL Parts Team) in September, 2014 –SEU, SEFI transient effects acceptable DCB implements ECC and resets each FLASH memory prior to any read or write operation Modules are usually powered off –SEFF onset threshold is in between LET of 40 and 60 MeV-cm2/mg. Rates were calculated based on the Worst Week Perihelion environment –For LET threshold at 40 MeV-cm2/mg: The SEFF rate is 4.34E-4 events/day (or 6.3 years/event) –For LET threshold at 60 MeV-cm2/mg: The SEFF rate is 6.99E-5 events/day (or 39.2 years/event) –Using worstcase LET threshold of 40 MeV-cm2/mg: »4.34E-4 events/day worst week is events/worst week »=> 0.3% chance of a SEFF per chip per mission (one worst week event during perihelion) »probability even less due to small power-on duty cycle (FIELDS only powers 1/4 of the array at a time, and only for.25 sec about every 30 seconds) –Further testing of SEFF failed die planned –Determine if the failure of one device in a stacked module could permanently disable the entire module 17