1 Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.

Slides:



Advertisements
Similar presentations
Arbitrary Waveform Discussion 5.5 Example 34.
Advertisements

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)
Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.
Logic Design Fundamentals - 3 Discussion D3.2. Logic Design Fundamentals - 3 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.
RS-232 Port Discussion D7.1. Loop feedback RS-232 voltage levels: +5.5 V (logic 0) -5.5 V (logic 1)
Integer Square Root.
Simple Sequential Circuits in VHDL. Contents Sequential circuit examples: - SR latch in dataflow style - D flip-flop in behavioral style - shift register.
Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.
Lab 6 Program Counter and Program ROM Mano & Kime Sections 7-1 – 7-6.
CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 3 Khurram Kazi Some of the slides were taken from K Gaj ’ s lecture slides from GMU ’ s VHDL.
Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.
VHDL And Synthesis Review. VHDL In Detail Things that we will look at: –Port and Types –Arithmetic Operators –Design styles for Synthesis.
7-Segment Displays Digilent Spartan 3 Board Discussion DS-4.2.
Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.
Introduction to VHDL Multiplexers Discussion D1.1.
Lab 3 & 4 Discussion EE414/514 VHDL Design September 25.
Registers Lab 5 Mano and Kime Sections 5-2, 5-3, 5-7.
RS-232 Port Lecture L9.3. Loop feedback RS-232 voltage levels: +5.5 V (logic 0) -5.5 V (logic 1)
4-Bit Binary-to-BCD Converter: case Statement
Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);
PS/2 Mouse/Keyboard Port Discussion D7.2. PS/2 Port.
4-bit Shift Register. 2-bit Register Serial-in-serial-out Shift Register.
Introduction to VHDL (part 2)
ECE 448: Lab 4 FIR Filters.
LAB 9 Finite State Machine (FSM) Ui Luu Glendale Community College Bassam Matar Chandler-Gilbert Community College.
1 Part V: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.
ECE 448: Spring 12 Lab Midterm Exam Review. Part 1: Detailed discussion of a selected midterm from Spring Part 2: Review & discussion of common.
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.
Design Verification VHDL ET062G & ET063G Lecture 5 Najeem Lawal 2012.
VHDL in 1h Martin Schöberl. AK: JVMHWVHDL2 VHDL /= C, Java,… Think in hardware All constructs run concurrent Different from software programming Forget.
A full die photograph of the MIPS R2000 RISC Microprocessor is shown above. The 1986 MIPS R2000 with five pipeline stages and 450,000 transistors was the.
VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f
Copyright(c) 1996 W. B. Ligon III1 Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component.
Reaction Timer Project
Mixed Style RTL Modeling
2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.
Chapter 5 Introduction to VHDL. 2 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.
1 RAM. 2 PS2_Keyboard: entity work.Keyboard generic map (AddressBits => ADDRESSLENGTH) port map (Reset => Reset, Clock => ClockVGA, PS2Clock => PS2Clock,
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.
VHDL Discussion Sequential Sytems. Memory Elements. Registers. Counters IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology.
 Seattle Pacific University EE Logic System DesignCounters-1 Shift Registers DQ clk DQ DQ ShiftIn Q3Q3 Q2Q2 DQ Q1Q1 Q0Q0 A shift register shifts.
1 Part III: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
CEC 220 Digital Circuit Design VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Slide 1 of 13.
George Mason University Controllers for Keccak_F and AES ECE 545 Lecture 11 Addendum.
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL VHDL Coding for Synthesis ECE 448 Lecture 12.
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.
Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.
CDA 4253 FPGA System Design Sequential Circuit Building Blocks Hao Zheng Dept of Comp Sci & Eng USF.
George Mason University Behavioral Modeling of Sequential-Circuit Building Blocks ECE 545 Lecture 8.
EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09.
Registers and Counters Discussion D8.1. Logic Design Fundamentals - 3 Registers Counters Shift Registers.
1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2.
Combinational logic circuit
CHAPTER 17 VHDL FOR SEQUENTIAL LOGIC
Part IV: VHDL CODING.
Software Environment ISE 5.x Interaction with simple LCDs
Behavioral Modeling of Sequential-Circuit Building Blocks
Founded in Silicon Valley in 1984
Sequntial-Circuit Building Blocks
Data Flow Description of Combinational-Circuit Building Blocks
Data Flow Description of Combinational-Circuit Building Blocks
VGA Display: VGA Synchronization & Pixel Generation
Sequntial-Circuit Building Blocks
High-Low Guessing Game
디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계
(Sequential-Circuit Building Blocks)
(Simple Testbenches & Arithmetic Operations)
Presentation transcript:

1 Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal

2 EA KIT240-7 (Electronic Assembly) Available: EA KIT Control panel with fonts, graphic commands and macros. Electronic Assembly, 2002: Pixels RS232 begins majority of commands (ASCII code 1B 16 ) the code of command (ASCII code ) Draws a straight line from the last end point to the point with coordinates (x1,y1) last end point x1 y1

3 rs_control provides the selected baud rate

4 subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word10; constant line_RS : serial_pac := ( x"1B", --delete display x"44", --delete display x"4C", --delete display x"1B", --draw line (ESC) x"47", --draw line (code of this operation) x"30",-- x1 left point x"15",-- y1 upper point x"E6",-- x2 right point x"72");-- y2 bottom point the first command the second command

5 subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word10; constant line_RS : serial_pac := (x"1B", x"44", x"4C", x"1B", x"47", x"30", x"15", x"E6", x"72"); “ ” start bit stop bit 8 data bits lclk if rising_edge(lclk) then RS232out <= line_RS(ind)(tmp); RS232in RS232out Begins any instruction x"1B"

6 case tmp is when 0 => my_out <= '0'; tmp := tmp + 1; when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp := tmp + 1; when 9 => my_out <= '1'; tmp := tmp + 1; when 10 => tmp := 0; ind := ind + 1; when others => tmp := 0; end case; RS232in RS232out 8 data bits start bit stop bit case tmp is when 0 => my_out <= '0'; tmp := tmp + 1; when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp := tmp + 1; when 9 => my_out <= '1'; tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind := ind + 1; when others => tmp := 0; end case; RS232out <= my_out; because LCD panel works slow

7 RS232in RS232out process(clk, rst) variable tmp, ind: integer; begin if rst= '1' then tmp:=0; ind :=0; elsif falling_edge(clk) then if rs232in = '0' then ind := 1; end if; if (tmp >= 1) then if (tmp <= 8) then LCD_symbol(tmp-1) <= rs232in; end if; if ind = 1 then tmp := tmp + 1; end if; if (tmp >= 9) and (rs232in = '1') then tmp := 0; ind := 0; end if; result <= LCD_symbol; end process; 8 data bits waiting for start bit receiving data bits waiting for stop bit received_ASCII

8 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity RS_control is Port (clk: in std_logic; rst: in std_logic; rin : instd_logic_vector(7 downto 0); result: outstd_logic_vector(7 downto 0); rs232in: in std_logic; rs232out: out std_logic); end RS_control; baud rate for the considered example is reset received_ASCII result from touch panel

9 architecture Behavioral of RS_control is subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word10; constant line_RS : serial_pac := ( x"1B", --delete display x"44", --delete display x"4C", --delete display x"1B", --draw line (ESC) x"47", --draw line (code of this operation) x"30",-- x1 left point x"15",-- y1 upper point x"E6",-- x2 right point x"72");-- y2 bottom point signal LCD_symbol : std_logic_vector (7 downto 0); signal my_out : std_logic;

10 begin process(clk, rst) variable tmp: integer; variable ind : integer; begin if rst= '1' then tmp:=0; ind := 0; my_out <= '1'; elsif rising_edge(clk) then if ind <= 8 then case tmp is when 0 => my_out <= '0';tmp := tmp + 1; when 1 to 8 =>my_out <= line_RS(ind)(tmp); tmp := tmp + 1; when 9 => my_out <= '1';tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind := ind + 1; when others => tmp := 0; end case; end if; RS232out <= my_out; end process;

11 process(clk, rst) variable tmp: integer; variable ind: integer; begin if rst= '1' then tmp:=0; ind :=0; elsif falling_edge(clk) then if rs232in = '0' then ind := 1; end if; if (tmp >= 1) then if (tmp <= 8) then LCD_symbol(tmp-1) <= rs232in; end if; if ind = 1 then tmp := tmp + 1; end if; if (tmp >= 9) and (rs232in = '1') then tmp := 0; ind := 0; end if; result <= LCD_symbol; end process; end Behavioral;

12 architecture Behavioral of RS_control is subtype test8 is std_logic_vector (7 downto 0); type test is array (7 downto 0) of test8; signal my_test : test; subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word10; constant line_RS : serial_pac := ( “ ", --delete display “ ", --delete display “ ", --delete display “ ", --draw line (ESC) “ ", --draw line (code of this operation) “ ",-- x1 left point “ ",-- y1 upper point “ ",-- x2 right point “ ");-- y2 bottom point signal LCD_symbol : std_logic_vector (7 downto 0); signal my_out : std_logic;

start bit data bits 1B stop bit subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word10; constant line_RS : serial_pac := ( “ ", --delete display “ ", --delete display “ ", --delete display -- ………………………………

15

16 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RS_divider is Port (clk48: in std_logic; rst: in std_logic; clockRS: out std_logic); end RS_divider; architecture Behavioral of RS_divider is signal lclk : std_logic; begin process(clk48, rst) variable temp: integer; begin if rst= '1' then temp:=0; lclk <= '0'; elsif rising_edge(clk48) then temp := temp + 1; if temp = 208 then lclk <= '1'; elsif temp > 417 or temp < 0 then lclk <= '0'; temp:=0; end if; end process; clockRS <= lclk; end Behavioral; 48 MHZ baud rate

17 Crossing was done inside the board RTS 5 CTS RS232/J3 (10 pins) RS232/9 pins grouund 5 10 ground User constraints NET "rs232out" LOC = "c12"; NET "rs232in" LOC = "b13";

18 Mode 1 (automatically) Mode 2 (dependently on switch)

19 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity RS_control is-- see slide 8 Port (clk: in std_logic; rst: in std_logic; rin : instd_logic_vector(7 downto 0); result: outstd_logic_vector(7 downto 0); rs232in: in std_logic; rs232out: out std_logic); end RS_control; architecture Behavioral of RS_control is signal LCD_symbol : std_logic_vector (7 downto 0); signal my_out : std_logic; signal lclk : std_logic_vector(19 downto 0); subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 21) of word10; Less significant bit, which allows to change the size of the rectangle internal signal to store the result internal signal to store an output for RS232 low frequency clock word10 allows to change the number of bits in the vectors if required Subtype is the same type as its base type. Assignment between subtype and base type objects can be made without conversion serial_pac contains 22 words (ASCII codes), which will be sent through RS232

20 constant line_RS : serial_pac := ( x"1B", --delete display x"44", --delete display x"4C", --delete display x"1B", --define a rectangle (ESC) | if rin = “0…0" x"42", --define a rectangle (code of this operation) x"52",-- extend to right x"01",-- number given to this rectangle x"2A",-- x1 x"2A",-- y1 x"7A",-- x2 x"4A",-- y2 x"04",-- start value ( ) x"84", -- end value ( ) x"04",-- number of pattern x"1B",-- draw the defined above rectangle (ESC) x"42",-- draw the defined above rectangle (code) x"01",-- number x"5A",-- new value in between start and end x"1B", -- draw the defined above rectangle (ESC) | if rin /= “ " x"42", -- draw the defined above rectangle (code) x"01", -- number x"3F"); -- new value in between start and end These 22 ASCII codes will be sent sequentially to RS232 beginning from the top code (1B 16 ) and ending by the bottom code (3F 16 ) LCD command clear display LCD command that defines (but does not draw) a bar (a rectangle). All the details are given in LCD command that draws the defined above rectangle

21 begin process(clk,rst) begin if rst = '1' then lclk '0'); elsif falling_edge(clk) then lclk <= lclk+1; end if; end process; process(clk, rst) variable tmp: integer; variable ind, ind1: integer; begin if rst= '1' then tmp:=0; ind:=0; ind1:=0; my_out<='1'; elsif rising_edge(clk) then if lclk(lclk'left) = '1' then -- rin = “ " then – use this italic line for the mode 2 if ind <= 17 then case tmp is when 0 => my_out <= '0';tmp:=tmp+1; when 1 to 8 =>my_out <= line_RS(ind)(tmp); tmp:=tmp+1; when 9 => my_out <= '1';tmp:=tmp+1; when 10 to 1500 =>tmp:=tmp+1; my_out<='1'; when 1501 => tmp:= 0; ind:=ind+1; ind1:=0; when others => tmp := 0; end case; end if; This process provides low frequency for changing sizes of the rectangles on the LCD in visual mode. This process can be removed for the second mode This block is executed for the first rectangle with larger size

22 else if ind1 <= 21 then case tmp is when 0 => my_out <= '0';tmp := tmp + 1; when 1 to 8 =>my_out <= line_RS(ind1)(tmp); tmp := tmp + 1; when 9 => my_out <= '1';tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind1 := ind1 + 1; ind := 0; when others => tmp := 0; end case; end if; RS232out <= my_out; end process; This block is executed for the second rectangle with smaller size

23 process(clk, rst) variable tmp: integer; variable ind: integer; begin if rst= '1' then tmp:=0; ind :=0; elsif falling_edge(clk) then if rs232in = '0' then ind := 1; end if; if (tmp >= 1) then if (tmp <= 8) then LCD_symbol(tmp-1) <= rs232in; end if; if ind = 1 then tmp := tmp + 1; end if; if (tmp >= 9) and (rs232in = '1') then tmp := 0; ind := 0; end if; result <= LCD_symbol; end process; end Behavioral; This process receives data from LCD, which can be generated when you touch the panel. This block will be needed for the next example (example 3) See slide 7

24 ABCD ADD ORT TEST 1 touch A ORT ADD TEST received_ASCII A 2 touch B received_ASCII B 3 touch A TEST ADD ORT received_ASCII A 4 touch C received_ASCII C ORT ADD TEST 5 touch D received_ASCII D touch B to reset a previous menu option

25 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity RS_control is Port (clk: in std_logic; rst: in std_logic; rin : instd_logic_vector(7 downto 0); result: outstd_logic_vector(7 downto 0); rs232in: in std_logic; rs232out: out std_logic); end RS_control; architecture Behavioral of RS_control is subtype word10 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 72) of word10; signal LCD_symbol : std_logic_vector (7 downto 0); signal my_out : std_logic;

26 constant line_RS : serial_pac := ( x"1B", --0 x"46", --1 x"05", --2 x"02", --3 x"01", --4 x"1B",--5 x"51",--6 x"43", --7 x"00",--8 x"1B",-- 9 std_logic_vector(to_unsigned(character'pos('D'), 8)),-- 10 std_logic_vector(to_unsigned(character'pos('L'), 8)),-- 11 x"1B", command ID x"54", initiation of touch command x"48", horizontal labeling x"01", upper left touch field x"0C", lower right touch field x"41", return code of the letter A x"02", drawing of key with frame x"41", drawing of letter A in the frame x"00", end of this command x"1B",--21 x"54",--22 x"48",--23 x"04",--24 x"0F",--25 x"42",--26 x"02",--27 x"42",--28 x"00",--29 sets font switches the cursor off clears the display (compare with the slide 20) similar command 0C 16 =12 10 received_ASCII A A B

27 x"1B",--30 x"54",--31 x"48",--32 x"07",--33 x"12",--34 x"43",--35 x"02",--36 x"43",--37 x"00",--38 x"1B",--39 x"54",--40 x"48",--41 x"0A",--42 x"14",--43 x"44",--44 x"02",--45 x"44",--46 x"00",--47 similar command ABCD

28 x"1B",-- command ID x"4E",-- display menu x"48",-- horizontal menu x"60",-- x for upper left corner x"30",-- y for upper left corner x"01",-- currently inverted item std_logic_vector(to_unsigned(character'pos('A'), 8)), std_logic_vector(to_unsigned(character'pos('D'), 8)), x"7C",-- separator std_logic_vector(to_unsigned(character'pos('O'), 8)), std_logic_vector(to_unsigned(character'pos('R'), 8)), std_logic_vector(to_unsigned(character'pos('T'), 8)), x"7C",-- separator std_logic_vector(to_unsigned(character'pos('T'), 8)), std_logic_vector(to_unsigned(character'pos('E'), 8)), std_logic_vector(to_unsigned(character'pos('S'), 8)), std_logic_vector(to_unsigned(character'pos('T'), 8)), x"00",-- separator x"1B",-- command ID x"4E",-- the next menu item is inverted x"1B", -- command ID x"4E", -- the previous menu item is inverted x"50"); -- the previous menu item is inverted ABCD ADD ORT TEST

29 begin process(clk, rst) variable tmp: integer; variable ind, ind1, ind2 : integer; begin if rst= '1' then tmp:=0; ind := 0; ind1 := 67; ind2 := 70;RS232out <= '1'; elsif rising_edge(clk) then if ind <= 66 then case tmp is when 0 => my_out <= '0';tmp := tmp + 1; when 1 to 8 =>my_out <= line_RS(ind)(tmp); tmp := tmp + 1; when 9 => my_out <= '1';tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind := ind + 1; when others => tmp := 0; end case; end if; if ind1 <= 69 then if LCD_symbol = x"41" then case tmp is when 0 => my_out <= '0';tmp := tmp + 1; when 1 to 8 =>my_out <= line_RS(ind1)(tmp); tmp := tmp + 1; when 9 => my_out <= '1';tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind1 := ind1 + 1; when others => tmp := 0; end case; end if; the values of these variables will be changed below in the process dependently on the code of a symbol received from touch panel of the LCD thus, different control subsequences will be activated

30 if ind2 <= 72 then if LCD_symbol = x"43" then case tmp is when 0 => my_out <= '0';tmp := tmp + 1; when 1 to 8 =>my_out <= line_RS(ind2)(tmp); tmp := tmp + 1; when 9 => my_out <= '1';tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind2 := ind2 + 1; when others => tmp := 0; end case; end if; if LCD_symbol = x"42" then ind1 := 67; ind2 := 70; end if; RS232out <= my_out; end process; if LCD_symbol = x"42" then ind1 := 67; ind2 := 70; end if;

31 process(clk, rst) variable tmp: integer; variable ind: integer; begin if rst= '1' then tmp:=0; ind :=0; elsif falling_edge(clk) then if rs232in = '0' then ind := 1; end if; if (tmp >= 1) then if (tmp <= 8) then LCD_symbol(tmp-1) <= rs232in; end if; if ind = 1 then tmp := tmp + 1; end if; if (tmp >= 9) and (rs232in = '1') then tmp := 0; ind := 0; end if; result <= LCD_symbol; end process; end Behavioral; This process receives data from LCD, which can be generated when you touch the panel. See slide 7 ABCD

32