Functional Coverage Jean-Michel Chabloz. Coverage Code coverage, expression coverage, etc. are automatically inferred Functional coverage specifies what,

Slides:



Advertisements
Similar presentations
CS 3850 Lecture 6 Tasks and Functions. 6.1 Tasks and Functions Tasks are like procedures in other programming languages. e. g., tasks may have zero or.
Advertisements

Traffic light contoller using FSM
Lecture 23: Registers and Counters (2)
Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.
Synchronous Sequential Logic
Combinational Logic.
Table 7.1 Verilog Operators.
Slide 1 7. Verilog: Combinational always statements. VHDL: Combinational Processes: To avoid (I.E. DO NOT What in your HDL code?) Cases that generate Synthesis.
Presented by: Omer Shaked Beeri Schreiber Serial Peripheral Interface Final Project Presentation Supervised by: Tal Yahav Leon Polishuk.
ECE 551 Digital System Design & Synthesis Lecture 09 Synthesis of Common Verilog Constructs.
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
ELEN 468 Lecture 81 ELEN 468 Advanced Logic Design Lecture 8 Behavioral Descriptions II.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
ELEN 468 Lecture 91 ELEN 468 Advanced Logic Design Lecture 9 Behavioral Descriptions III.
ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.
Assertions in OpenVera Assertions check for the occurrence of sequences during simulation Sequence is an ordered (maybe timed) series of boolean events.
ELEN 468 Advanced Logic Design
Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi.
Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks.
Timing control in verilog Module 3.1 Delays in Verilog.
Design Synopsys System Verilog API Donations to Accellera João Geada.
Overview Logistics Last lecture Today HW5 due today
Sequential Logic in Verilog
1 Verilog Digital System Design Z. Navabi, 2006 Digital Design Flow  Digital Design Flow begins with specification of the design at various levels of.
Synthesis Presented by: Ms. Sangeeta L. Mahaddalkar ME(Microelectronics) Sem II Subject: Subject:ASIC Design and FPGA.
SoC Verification HW #2 TA: Wei-Ting Tu Assignment: 04/12/06
Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 4-1 Ders – 4: Davranışsal Modelleme.
ECE 551 Digital System Design & Synthesis Fall 2011 Midterm Exam Overview.
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
Introduction to OVL (Open Verification Library) Alexander Gnusin.
Slide 1 6. VHDL/Verilog Behavioral Description. Slide 2 Verilog for Synthesis: Behavioral description Instead of instantiating components, describe them.
Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 7: Design Example, Modeling Flip-Flops Spring.
Design Verification Code and Toggle Coverage Course 7.
1 COMP541 Sequential Circuits Montek Singh Feb 1, 2012.
Assertions Jean-Michel Chabloz. Assertions basic Idea We assert that a certain “thing” should be true. –If it is true, fine –If it is false, then we get.
Final Project. System Overview Description of Inputs reset: When LOW, a power on reset is performed. mode: When LOW, NORMal mode selected When HIGH,
Digital System Design Verilog ® HDL Behavioral Modeling Maziar Goudarzi.
Behavioral Modelling - 1. Verilog Behavioral Modelling Behavioral Models represent functionality of the digital hardware. It describes how the circuit.
M.Mohajjel. Structured Procedures Two basic structured procedure statements always initial All behavioral statements appear only inside these blocks Each.
M.Mohajjel. Objectives Learn How to write synthesizable Verilog code Common mistakes and how to avoid them What is synthesized for what we code Digital.
 A test bench is an HDL program used for applying stimulus to an HDL design in order to test it and observe its response during simulation.  In addition.
03/31/031 ECE 551: Digital System Design & Synthesis Lecture Set 8 8.1: Miscellaneous Synthesis (In separate file) 8.2: Sequential Synthesis.
Verilog® HDL Behavioral Modeling (2)
Synchronous Counter Design
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
1 University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
1 Modeling Synchronous Logic Circuits Debdeep Mukhopadhyay Associate Professor Dept of Computer Science and Engineering NYU Shanghai and IIT Kharagpur.
Lecture 5. Verilog HDL #3 Prof. Taeweon Suh Computer Science & Engineering Korea University COSE221, COMP211 Logic Design.
EMT 351/4 DIGITAL IC DESIGN Verilog Behavioral Modeling  Constructs for Activity Flow Control  Task & Function  System Tasks for Timing Checks.
Overview Logistics Last lecture Today HW5 due today
An Introduction to Verilog: Transitioning from VHDL
Supplement on Verilog FF circuit examples
Figure 8.1. The general form of a sequential circuit.
Last Lecture Talked about combinational logic always statements. e.g.,
EMT 351/4 DIGITAL IC DESIGN Week # Synthesis of Sequential Logic 10.
Digital System Verification
SYNTHESIS OF SEQUENTIAL LOGIC
Developing More Advanced Testbenches
SystemVerilog Implementation of GCD
Chapter 4: Behavioral Modeling
Test Fixture (Testbench)
Lecture 9: Testbench and Division
The Verilog Hardware Description Language
Lecture 4: Continuation of SystemVerilog
ECE 551: Digital System Design & Synthesis
332:437 Lecture 9 Verilog Example
332:437 Lecture 9 Verilog Example
332:437 Lecture 9 Verilog Example
Lecture 7: Verilog Part II
Presentation transcript:

Functional Coverage Jean-Michel Chabloz

Coverage Code coverage, expression coverage, etc. are automatically inferred Functional coverage specifies what, how and when to gather cover data. Normally the verification plan contains coverage objectives. These get translated into functional coverage, so that when 100% coverage is reached, the verification work is considered complete

Functional coverage – with triggering event bit [1:0] b; covergroup clk); bcov: coverpoint b; endgroup cg cg_inst = new Always sample, on every negative clock edge, the value of b. At the end of the simulation we can get the results in the form: 125 times b was 00, 48 times b was 01, 70 times b was 10, 113 times b was 11. If b never was 01, then we have a coverage hole (75% coverage only). It’s possible to specify a minimal amount of hits for a bin to be considered as covered – if the limit is 3 and az bin is hit only twice, there’s a coverage hole.

Functional coverage – no triggering event bit [1:0] b; covergroup cg; bcov: coverpoint b; endgroup cg cg_inst = new; //declare and instantiate a c.group initial begin repeat(10) end // do something if (condition) cg_inst.sample(); ##1; end

Enabling condition covergroup clk); bcov: coverpoint b iff (c==4); endgroup Record coverage on b on every negative clock edge, only if c==4, otherwise ignore (don’t sample). Can be used in covergroups with or without triggering events iff can be used on any coverpoint, on any covergroup. Typical usage: deactivate coverage when reset is low

Automatic bins bit [1:0] b; enum{a,b,c} letter; covergroup clk); bcov: coverpoint b; lettercov: coverpoint letter; endgroup Creates 4 bins for bcov, 3 for lettercov (one for every possible value) for 4-valued data types, X and Z are never recorded bins are like counters: every time the covergroup is triggered and the variable has a certain value, the bin is incremented by one

Automatic bins integer i; enum{a,b,c} letter; covergroup clk); icov: coverpoint i; endgroup There is a maximal number of automatically-created bins, by default If the number of values a coverpoint can take is above 1024, the set of all possible values is automatically “sliced” In this case 1024 bins will be created – with MAXINT=2^32: [0, …, MAXINT/1024-1] [MAXINT/1024, …, 2*MAXINT/1024-1] … [1022*MAXINT/1024, …, 1023*MAXINT/1024-1] [1023*MAXINT/1024, …, MAXINT-1]

bins It is possible to specify bins instead of using automatic bins bit [9:0] v_a; covergroup clk); coverpoint v_a { bins a = { [0:63],65 }; // values from 0 to 63 or 65 bins b[] = { 200,201,202 }; // creates 3 bins bins c = { [1000:$] }; // from 1000 to 1023 bins d[] = { [10:14], [16:18]}; // creates 7 bins bins others = default; // everything else } endgroup a: 1 bin, incremented if v_a is 65 or is between 0 and 63 b: 3 bins, each is incremented when v_a takes values 200, 201, 202 c: 1 bin, incremented when v_a is between 1000 and 1023 d: 7 bins, each is incremented when v_a takes values 10, 11, 12, 13, 14, 16, 17, 18 others: 1 bin, incremented when v_a takes any value that is not covered by the other bins

wildcard bins Another way of specifying bins, introduced with the keyword “wildcard”. wildcard bins a={11xx}; –hits for 1100, 1101, 1110 and 1111 As a symbol for wildcard, we can use –x –z –?

ignore bins covergroup clk); coverpoint v_a { ignore_bins ib = {0, 1, 2}; bins three ={3}; bins four = {4}; } endgroup We don’t care about when v_a takes the values 0, 1, 2 These values are excluded from coverage The tool won’t signal any lack of coverage if v_a never was 0, 1 or 2. If v_a never was 3, however, then bin three is uncovered – coverage hole Can be useful for values that the testbench should never generate Example: the testbench generates random even numbers, all odd numbers can be defined as ignore_bins.

illegal bins covergroup clk); coverpoint v_a { illegal_bins ib = {0, 1, 2}; bins three ={3}; bins four = {4}; } endgroup If v_a takes the values 0, 1 or 2 we get a run-time error. Can be useful for values that the DUT should never generate Example: if the DUT should give in output an even number, all odd numbers can be defined as illegal_bins. If an odd number is encountered, it means there is a bug in the DUT.

Cross coverage bit [3:0] a, b; covergroup clk); aXb : cross a, b; endgroup 16x16 automatic bins, one for each combination of values of a and b –how many times a was 0 and b was 0 in the same cycle? –how many times a was 0 and b was 1 in the same cycle? –… –how many times a was 15 and b was 14 in the same cycle? –how many times a was 15 and b was 15 in the same cycle?

Automatic cross bins If bins are unspecified, one bin for every combination of values is generated automatically enum { red, green, blue } color; bit [3:0] pixel_adr, pixel_offset, pixel_hue; covergroup clk); Hue: coverpoint pixel_hue; // 16 bins Offset: coverpoint pixel_offset; // 16 bins AxC: cross color, pixel_adr; // 3*16 bins all: cross color, Hue, Offset; // 3*16*16 bins endgroup

Cross coverage bit [31:0] a_var; bit [3:0] b_var; covergroup clk); A: coverpoint a_var { bins yy[] = { [0:9] }; } CC: cross b_var, A; endgroup cross between one variable and one coverpoint 16x10 bins in CC.

Specifying bins in cross coverage bit [7:0] v_a, v_b; covergroup clk); a: coverpoint v_a { bins a1 = { [0:63] }; bins a2 = { [64:127] }; bins a3 = { [128:191] }; bins a4 = { [192:255] }; } b: coverpoint v_b { bins b1 = {0}; bins b2 = { [1:84] }; bins b3 = { [85:169] }; bins b4 = { [170:255] }; } c : cross a, b // 16 bins { bins c1 = !binsof(a.a4); // 12 bins illegal_bins c2 = binsof(a.a2) || binsof(b.b2);// 7 cross products ignore_bins c3 = binsof(a.a1) && binsof(b.b4);// 1 cross product } endgroup

Transition bins Bins used to specify transitions of values from one sampling time to a future one. bins a = (value1 => value2): counts how many times the variable had value1 and in the following sampling time had value2 bins a = (1 => 3 => 4): var had value 1, then 3, then 4. bins a = (1,5 => 6, 7): var had value 1 or 5 and in the next sampling time value 6 or 7 (transitions 1=>6, 1=>7, 5=>6, 5=>7)

Transition bins bins sa = (4 => 5 => 6), ([7:9],10=>11,12); one bin only is created, it is incremented for the following transitions: –4=>5=>6 –7=>11 –8=>11 –9=>11 –10=>11 –7=>12 –8=>12 –9=>12 –10=>12

Transition bins bins sa[] = (4 => 5 => 6), ([7:9],10=>11,12); 9 bins are created, they are respectively incremented for the following transitions: –4=>5=>6 –7=>11 –8=>11 –9=>11 –10=>11 –7=>12 –8=>12 –9=>12 –10=>12

Transition bins wildcard bins T0 = (2’b0x => 2’b1x); –increments for 00 => 10; 01 => 10; 00 => 11; 01 => 10;

Transition bins support illegal and ignore bins illegal_bins bad_trans = (4=>5=>6); ignore_bins bad_trans = (4=>5=>6);

Transition bins - Repetition (3 [*3]) is equivalent to (3 => 3 => 3) Note: if we have four consecutive times 3, then the bin will receive two hits. (3 [*3:5]) is equivalent to (3 => 3 => 3), (3 => 3 => 3 => 3), (3 => 3 => 3 => 3 => 3)

Transition bins - Repetition (2 => 3 [*3] => 1) is equivalent to –(2 => 3 => 3 => 3 => 1) (1 => 3 [*3:5]) is equivalent to (1=>3=>3=>3),(1=>3=>3=>3=>3),(1=>3=>3=>3=>3=>3)

Transition bins - Repetition (1 => 3 [*4:$] => 2) hits every time there is a 1 followed by at least 4 times 3, followed by a 2.

Goto repetition Advanced type of repetition: 3 [-> 3] is equivalent to …=>3=>…=>3=>…=3 where … is any transition of any length that does not contain the value 3. 1 => 3 [ -> 3] => 5 is equivalent to 1 => … => 3 => … => 3 => … => 3 => 5