EEE 348E INTRODUCTION TO IC DESIGN P.M Dr Othman Sidek (Director of CEDEC) Mr. Arjuna Marzuki (room 2.15, ext: 6021) Instructor/Tutor Ruhaifi

Learning Outcomes  Students will be able to design and simulate logic circuits at transistor level using schematic entry as well as netlists format.  Students will be able to produce the layout design of a circuit based on the design rules specified.  Students will be able to analyze CMOS transistor characteristics.  Students will be able present their mini project individually in a viva session.

Laboratory (CEDEC Lab) Lab 1, Week3 : Netlist Lab 2, Week4 : Schematic design Lab 3, Week5 : Layout design Lab 4, Week6 : DRC and LVS Week7 – 13 : Mini Project Week14 : Viva & Presentation

CAD Tools Cadence (Linux OS): Text Editor - Netlist Schematic Composer - Schematic Virtuoso - Layout Spectre- Simulation DIVA DRC- DRC DIVA LVS- LVS

Reading Lists 1) Kang, Sung-Mo and Leblebici, Yusuf, CMOS Digital Integrated Circuits- Analysis and Design, McGraw-Hill, 2005 (Text book). 1) Hodges, David A. et al, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, Mc- Graw-Hill, ) Neil H.E. Weste and Daid Harris, CMOS VLSI Design- A Circuits and Systems Perspective, Prentice Hall, ) Uyemura, J. P., Introduction to VLSI Circuits and Systems, John Wiley, ) Rabaey, J. M. et al, Digital Integrated Circuits – A Design Perspective, 2nd Edition, Prentice Hall, 2002.

Evaluation Course Work– 40% Assignments (3): 10% Mini project & Lab : 35% Final Exam – 60%

EXPECTATIONS  Attend classes and labs.  Find out what you’ve missed if you’re absent.  Come earlier than the lecturer/tutors..  Ask lecturer/tutor whenever have any problems related with the subject.

WHAT IS IC? ICs on PCB IC Package Inside IC Wafer

= = IC Layout IC Schematic

Why VLSI? Integration improves the design Lower parasitics = higher speed Lower power consumption Physically smaller Integration reduces manufacturing cost - (almost) no manual assembly