Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Switch networks. n Combinational testing.

Slides:

Advertisements

Similar presentations

Switching circuits Composed of switching elements called “gates” that implement logical blocks or switching expressions Positive logic convention (active.

Advertisements

Topics Electrical properties of static combinational gates:

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Gate Design n Static complementary logic gate structures. n Switch logic. n Other.

Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n State assignment. n Power optimization of sequential machines. n Design validation.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Memory elements. n Basics of sequential machines.

LEONARDO INSIGHT II / TAP-MM ASTEP - Basic Test Concepts © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Basic test concepts J. M. Martins.

Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei ECE 300 Advanced VLSI Design Fall 2006 Lecture 24: CAD Systems &

TOPIC : Backtracking Methodology UNIT 3 : VLSI Testing Module 3.2: Arriving at Input Test Vector.

A Look at Chapter 4: Circuit Characterization and Performance Estimation Knowing the source of delays in CMOS gates and being able to estimate them efficiently.

Copyright 2001, Agrawal & BushnellDay-1 AM-3 Lecture 31 Testing Analog & Digital Products Lecture 3: Fault Modeling n Why model faults? n Some real defects.

Logic Simulation 4 Outline –Fault Simulation –Fault Models –Parallel Fault Simulation –Concurrent Fault Simulation Goal –Understand fault simulation problem.

Modern VLSI Design 2e: Chapter 4 Copyright  1998 Prentice Hall PTR Topics n Switch networks. n Combinational testing.

Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.

Lecture 5 Fault Modeling

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault.

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Basic test concepts J. M. Martins Ferreira FEUP / DEEC - Rua Dr.

Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 14 - Testing.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

ELEN 468 Lecture 231 ELEN 468 Advanced Logic Design Lecture 23 Testing.

Silicon Programming--Physical Testing 1 Testing--physical faults: yield; s-a-0 and s-a-1 faults; justify and propagate.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Combinational logic functions. n Static complementary logic gate structures.

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Fault Modeling.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Interconnect design. n Crosstalk. n Power optimization.

Chapter 07 Electronic Analysis of CMOS Logic Gates

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Topics n Sequential machine (§5.2, §5.3) n FSM construction.

Unit I Testing and Fault Modelling

Chapter 7. Testing of a digital circuit

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Combinational network delay. n Logic optimization.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Pseudo-nMOS gates. n DCVS gates. n Domino gates.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Interconnect design. n Crosstalk. n Power optimization.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

4. Combinational Logic Networks Layout Design Methods 4. 2

VLSI Design Lecture 5: Logic Gates Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Wayne Wolf’s lecture notes.

ECE 260B – CSE 241A Testing 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Testing Website:

Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA

Topics Combinational network delay.

TOPIC : Different levels of Fault model UNIT 2 : Fault Modeling Module 2.1 Modeling Physical fault to logical fault.

Nonlinear & Neural Networks LAB. CHAPTER 8 Combinational Circuit design and Simulation Using Gate 8.1Review of Combinational Circuit Design 8.2Design of.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip.

EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University

Fault modeling is the translation of physical defects into a mathematical construct that can be operated upon algorithmically and.

An introduction to Fault Detection in Logic Circuits By Dr. Amin Danial Asham.

CS/EE 3700 : Fundamentals of Digital System Design

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Combinational network delay. n Logic optimization.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;

Manufacture Testing of Digital Circuits

Jan. 26, 2001VLSI Test: Bushnell-Agrawal/Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault models.

TOPIC : Introduction to Faults UNIT 2: Modeling and Simulation Module 1 : Logical faults due to physical faults.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Transistor sizing: –Spice analysis. –Logical effort.

TOPIC : Fault detection and fault redundancy UNIT 2 : Fault modeling Module 2.3 Fault redundancy and Fault collapsing.

VLSI Testing Class Fault Modeling 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault.

©2010 Cengage Learning SLIDES FOR CHAPTER 8 COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES Click the mouse to move to the next page. Use the ESC.

1 VLSI Design Lecture Four Design & Testing Issues Dr. Richard Spillman PLU Spring 2003.

VLSI Testing Lecture 5: Logic Simulation

VLSI Testing Lecture 5: Logic Simulation

Lecture 8 Combinational Network Design and Issues

Algorithms and representations Structural vs. functional test

NAND-ONLY LOGIC CIRCUITS

Lecture 5 Fault Modeling

Automatic Test Generation for Combinational Circuits

Topics Switch networks. Combinational testing..

VLSI Testing Lecture 3: Fault Modeling

ELEC Digital Logic Circuits Fall 2015 Logic Testing (Chapter 12)

Presentation transcript:

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Switch networks. n Combinational testing.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Boolean functions and switches pseudo-AND pseudo-OR

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Driving switch outputs n If switch network output is not connected to power supply through switch path, output will float. n Switch network inputs may be connected to power supply or logic signals.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Switching logic signals b’ a b a’ ab’ + a’b

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Switch multiplexer

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge sharing n Interior nodes in a switch network may not be driven. n Charge can accumulate on small parasitic capacitances. n Shared charge can produce erroneous output values.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge division n At undriven nodes, charge is divided according to capacitance ratio.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge sharing example n Long chains of switches have intermediate nodes which may be disconnected from power supplies. C ab C ia C bc

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge over time timeiC ia aC ib bC bc cC /211/ /203/413/ /403/ /813/803/4

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Avoiding charge sharing n Make sure that for every input combination there is a path from the power supply to the output.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Manufacturing testing n Errors are introduced during manufacturing. n Testing verifies that chip corresponds to design. n Varieties of testing: –functional testing; –performance testing (binning chips by speed). n Testing also weeds out infant mortality.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing and faults n Fault model: –possible locations of faults; –I/O behavior produced by the fault. n Good news: if we have a fault model, we can test the network for every possible instantiation of that type of fault. n Bad news: it is difficult to enumerate all types of manufacturing faults.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-at-0/1 faults n Stuck-at-0/1: logic gate output is always stuck at 0 or 1, independent of input values. n Correspondence to manufacturing defects depends on logic family. n Experiments show that 100% stuck-at-0/1 fault coverage corresponds to high overall fault coverage.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing procedure n Testing procedure: –set gate inputs; –observe gate output; –compare fault-free and observed gate output. n Test vector: set of gate inputs applied to a system.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-at faults in gates abOKSA0SA abOKSA0SA NAND NOR

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing single gates n Three ways to test NAND for stuck-at-0, only one way to test it for stuck-at-1. n Three ways to test NOR for stuck-at-1, only one way to test it for stuck-at-0.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing combinational networks n 100% coverage: test every gate for –stuck-at-0; –stuck-at-1. n Assume that there is only one faulty gate per network. n Most networks require more than one test vector to test all gates.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Multiple test example

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Example n Can test both NANDs for stuck-at-0 simultaneously (abc = 000). n Cannot test both NANDs for stuck-at-1 simultaneously due to inverter. Must use two vectors. n Must also test inverter.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-at-open/closed model n Models transistors always on/off.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-open behavior n If t 1 is stuck open (switch cannot be closed), there can be no path from V DD to output capacitance. n Testing requires two cycles: –must discharge capacitor; –try to operate t 1 to see if capacitor can be charged.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Delay fault n Delay falls outside acceptable limits: –gate delay fault assumes that all delays are lumped into one gate; –path delay fault models delay problems along path through network. n Delay problems reduce yield: –performance problems; – functional problems in some types of circuits.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Combinational network testing Two parts to testing: –controlling the inputs of (possibly interior) gates; –observing the outputs of (possibly interior) gates.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Combinational testing example

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing procedure n Goal: test gate D for stuck-at-0 fault. n First step: justify 0 values on gate inputs. n Work backward from gate to primary inputs: –w1 = 0 (A output = 0); –i1 = i2 = 1.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing procedure, cont’d n Observe the fault at a primary output: –o1 gives different values if D is true/faulty. n Work forward and backward: –F’s other input must be 0 to detect true/fault. –Justify 0 at E’s output. n In general, may have to propagate fault through multiple levels of logic to primary outputs.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Fault masking Redundant logic can mask faults:

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Redundancy example n Testing NOR for SA0 requires setting both inputs to 0. n Network topology ensures that one NOR input will always be 1. n Function reduces to 0: –f = (ab)’ + b’ = a’ + b’ + b = 0.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Redundancies and testing n Redundant logic cannot be controlled. n Observations requiring control of redundant logic may not be possible. n Redundant logic should be minimized to eliminate redundancy. Redundancies can introduce delay faults and other problems.