Research in IC Packaging Electrical and Physical Perspectives

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Presentation transcript:

Research in IC Packaging Electrical and Physical Perspectives Chung-Kuan Cheng CSE Department UC San Diego La Jolla, CA 92093-0404 ckcheng@ucsd.edu

Outline Short Biography Research Direction Challenges in IC Packaging Potential Areas for Co-operation Conclusion

Short Biography Ph.D., UC Berkeley,1984 Senior CAD Engineer, AMD, 1984-1986 Professor, UC San Diego, 1986-Present Chief Scientist, Mentor Graphics, 1998-1999 IBM Faculty Award, 2004, 2006 IEEE Fellow, 2000 Best Paper Awards, IEEE TCAD 1997, 2002 Excellence in Teaching, JSOE 1991 9 Patents (Pending), 2 Books, 175 papers 30 Ph.D. students, 15 Visiting Scholars

Research Directions Synthesis (Power & Performance) Networks on Chip Power, Clock Distribution, Global Interconnect Data Path Synthesis: Adders, Shifter, Multipliers, Division Operators Interconnect Technologies Packaging, MCM, Board, Interface Simulation (Whole Chip Analysis) SPICEDiego (Released by UCSD)

Challenges in IC Packaging Minimize power/ground fluctuations and simultaneous switching noise (SSN) in the package Control crosstalk and parasitic RLC Include chip and board interfaces in the design process (co-design) Use modeling and simulation tools to accurately predict and optimize performance Design a convenient and accurate platform to characterize performance Design novel packaging systems

Potential Areas of Co-operation Power/ground networks to minimize fluctuations and reduce SSN On-package decoupling capacitors Pin assignment and breakaway routing to minimize noise Electrical characterization of packages

Area #1 and #2 – Power/Ground Networks Spatial and temporal excitations Power ground distribution from board, packages, to chips. IR Drop: Static Analysis Resistive Networks Static Current Sources dI/dt: Dynamic Analysis RLC Networks Power on and off Sleep mode on and off Gated clocks Various operation modes

Area #1 and #2 - Power/Ground Network Analysis: Natural Frequency RLC Network Characteristics: Natural frequencies (Quality Factor) Operation Modes: Excite the resonance Decoupling Capacitance: Shift the natural frequencies.

Howard Chen, IBM

Area #3 - Pin Breakaway and Pin Assignment Obj: min noise Design Space Pin assignment of power ground pins and signal pairs Breakaway sequences Breakaway patterns

Area #3 - Pin Breakaway and Pin Assignment Row by Row Escape: Escape interconnect row by row from outside toward inside.

Area #3 – Pin Breakaway and Pin Assignment Central Triangular Escape: Escape objects from the center of the outside row and expands the indent with a single triangular outline.

Area #4 – Electrical Characterization Electrical characterization necessary in order to validate simulation results Especially critical at fast edge rates and high frequencies. Test vehicle design to include package mounted on a PCB that simulates the actual end product Time domain (TDR) and frequency domain (Network Analyzer) characterization Correlation to simulated results

UCSD Lab and Software Resources Cal IT2 Atkinson Hall at UCSD Sigrity Suite: Speed2000, PowerSI, PowerDC, BBS Agilent ADS (Advanced Design System) IBM EIP (Electrical Interconnect and Packaging) HSpice, SPICEDiego

Conclusion Goals of IC Package Design: High Performance High Quality Low Power, Cost Research collaboration between UCSD and Qualcomm can result in ways of improving performance Theoretical knowledge in UCSD Practical knowledge in Qualcomm