Silicon Solutions for the Real World 1 AID-EMC Automotive IC Design for Low EMC Review Meeting 29 augustus 2006 VILVOORDE.

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Presentation transcript:

Silicon Solutions for the Real World 1 AID-EMC Automotive IC Design for Low EMC Review Meeting 29 augustus 2006 VILVOORDE

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 2 Agenda Structure of the IWT project Progress per workpackage WP1: WP2: WP3: WP4: Status Deliverables Resources used Cooperation Conclusions

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 3 Structure of the project

Silicon Solutions for the Real World 4 WP1: Specifications and measurements

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 5 WP1: Technical problems Nearly impossible to achieve

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 6 T1.1: Correlation between different test set-ups Target is to increase current handling

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 7 T1.2: Influence of PCB and attached cabling VDMOS is more stable and robust

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 8 T1.3: Validation of the ICEM model Need for additional Selection

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 9 T1.4: Characterization of the coupling paths Need for additional Selection

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 10 T1.5: Measurements Need for additional Selection

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 11 Contributions by partners AMIS Aa bb KUL-ESAT aa KHBO cc

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 12 WP1: Innovation Realised Improved

Silicon Solutions for the Real World 13 WP2: EMC susceptibility of analogue circuits

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 14 WP2: Technical problems LDMOS Surface

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 15 T2.1: Finalization of the LIN driver Design Use

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 16 T2.2: Design DC current regulator with low EMS ESD

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 17 T2.3: Design input structure with low EMS Optimize

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 18 T2.4: Design input structure with high common mode rejection Optimize

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 19 T2.3: Design guidelines for low EMS Optimize

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 20 Contributions by partners AMIS Aa bb KUL-ESAT aa KHBO cc

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 21 WP2: Innovation Realised New Better Guidelines Technical Risks Protection

Silicon Solutions for the Real World 22 WP3: Digital techniques

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 23 WP3: Technical problems Logic families with reduced current variation how logic circuits can be designed in such a way that they generate less current variation (di/dt) in the supply lines EMC-friendly clock strategy how the electromagnetic radiation caused by digital circuits can be reduced by adapting the clock strategy.

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 24 T3.1: Design of EMC-friendly logic families - I Selection of EMC-friendly logic family: 6 different logic design techniques are compared, The design goal is to reduce di/dt noise while still keep the compromise on the speed, power, area trade-off under control, Based on the simulations, we conclude that CSL logic is the best choice. Comparison of CSL and SCMOS: The CSL logic produces an amount of di/dt noise almost 36dB smaller than the SCMOS logic, If controlled properly, we can keep the power of CSL circuit comparable to the SCMOS, CSL show a smaller area per logic function for complex digital gates and systems.

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 25 T3.1: Design of EMC-friendly logic families - II Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Ring Oscillator of 21-stages (Static + Dynamic) Current Steering Logic But there is static power !! di/dt Peak-Peak Power Area

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 26 T3.1: Design of EMC-friendly logic families - III Power spectrum density of di/dt comparison SCMOS CSL 36dB

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 27 T3.2: EMC-friendly clock strategies - I Clock skew Clock skew: based on the introduction of different skews to the branches of a clock tree. Only 2-5dB reduction, Need smart algorithm to control and optimize the skew. Spread Spectrum Clock Generation(SSCG) Spread Spectrum Clock Generation(SSCG): based on an existing DLL idea. Spread the clock period by a programmable amount, Fully digital and simple implementation, More than 12dB on the maximum di/dt power spectrum reduction. 2 different clock strategies are studied:

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 28 T3.2: EMC-friendly clock strategies - II Spectrum from 300MHz to 800MHz Spread Spectrum Clock Regular Clock 12dB reduction Zoom in A test chip for SSCG will be designed to prove the simulation(next project phase). Problem remains: introduction into a standard design flow.

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 29 T3.3: Test chip for the EMI Suppressing Regulator - I The EMI suppressing regulator replaces the EMC-friendly logic: Control the way the current delivered to the internal digital core, hence keep the EMI under control, Compatible with conventional CMOS logic, Large EMI reduction is ensured (40dB), comparable with low noise digital cells only, More power efficient than low noise logic cells, Can be adjusted to a wide range of chip size and power consumption level.

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 30 T3.3: Test chip for the EMI Suppressing Regulator - II current of Vbat di/dt p-p =8.5x10 4 [A/s] load current of digital core FFT di/dt p-p =1.8x10 9 [A/s] di/dt of Vbat di/dt of V3v3 40dB (EMI regulator) + 20dB (Serial regulator) 9x10 6 7x10 3

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 31 T3.3: Test chip for the EMI Suppressing Regulator - III Micrograph of the RD2E test chip and the EMI suppressing regulator EMI Suppressing regulator

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 32 T3.3: Test chip for the EMI Suppressing Regulator - IV Measurements > 5x reduction TBD: figure out low current capability problem, detailed measurements will be ready in 2nd phase

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 33 Contributions by partners AMIS Deliver specifications for the chip, Deliver design kit, Process the chip, Evaluate the chip measurement results. KUL-ESAT-MICAS Scientific analysis, Chip design, Chip measurements. KHBO Advice on the EMC measurements.

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 34 WP3: Innovation Realized Innovative characters: It addresses the problem of electromagnetic radiation at its very source, A systematic approach for radiation reduction is developed (includes a EMI suppressing regulator). A clever clock design strategy to guarantee low EMI is designed.

Silicon Solutions for the Real World 35 WP4: Computer-aided EMC analysis

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 36 WP4: Technical problems Technical problem

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 37 T4.1: Models for EMS simulation framework Improve

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 38 T4.2: Development of EMS simulation framework Design

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 39 T4.3: Automated generation of EM- inclusive behavioral models The best

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 40 T4.4: Industrial EMC design flow The best

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 41 Contributions by partners AMIS Aa bb KUL-ESAT aa KHBO cc

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 42 WP4: Innovation Realised Self-protecting Know-how Design guidelines Technical risks Conflicting aaa

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 43 Status Deliverables Main result:

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 44 Cooperation Flemish partners KUL ESAT KHBO AMIS

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 45 Resources (1)

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 46 Resources (2)

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 47 Conclusions 38% basis funding percentage

AID-EMC review meeting 29/08/2006CONFIDENTIAL Slide 48 Silicon Solutions for the Real World!