THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

DIGITAL GATES Fundamental Parameters The key parameters that govern a digital gate’s performance and usability. Area and Complexity Functionality and Robustness (Reliability) Performance Speed (delay) Power Consumption (dissipation) Energy The key parameters that govern a digital gate’s performance and usability.

Area and Complexity Small area very desirable for digital gate higher integration density smaller die size lower fabrication cost faster (smaller Cg) Implementation area depends on number of transistors interconnection area A gate should occupy the smallest area on a chip as possible. This relates directly to the ultimate cost of the chip.

Functionality and Robustness Prime requirement for digital gate: perform designed function Measured behavior deviates from expected response. Why? variations in process noise (unwanted variations of voltages and currents at the logic nodes) Logic levels VOH and VOL represent high and low logic levels difference is called the logic swing Process variations and noise hinder the performance of a gate from what it was initially designed for. We define logic levels to represent binary ‘0’ and ‘1’.

Noise in Digital Integrated Circuits V DD v ( t ) i (a) Inductive coupling (b) Capacitive coupling c) Power and ground noise Slide shows mechanisms by which unwanted noise is introduced to the input of a gate. While these effects cannot be avoided completely, they can be significantly reduced by employing good design techniques.

The Voltage-Transfer Characteristic Electrical function of gate is best expressed by its voltage-transfer characteristic (VTC) (DC transfer characteristic) Plots Vout =f(Vin) Gate (Switching) logic threshold voltage, VM: VM=f(VM) intersection of VTC at Vout=Vin The Voltage Transfer Characteristic describes the electrical function of the gate.

DC Operation: Voltage Transfer Characteristic (VTC) The Voltage Transfer Characteristic (VTC)

Mapping between analog and digital signals Problem: Output signal deviates from expected nominal value due to: noise loading of the gate output Solution: Logic levels represented by range of acceptable values Regions of acceptable values delimited by VIH and VIL represents points in VTC where (dVout/dVin) = -1 undefined region known as transition width Without representing the logic values as single values, but rather as a range of values, deviations from the nominal values can be compensated. The input logic values VIH and VIL are defined at the points where the gradient of the transfer characteristic equals -1.

Mapping between analog and digital signals The overlap between the nominal input voltage (say, VIL) and the nominal output voltage (VOL) creates a region that can be used to represent the logic value.

Noise Margins Measure of a gate sensitivity to noise Quantize the size of legal “0” and “1” Represents level of noise that can be tolerated when gates are cascaded NML (noise margin low) NML = VIL - VOL NMH (noise margin high) NMH = VOH - VIH Should be large as possible for good noise immunity The noise margin is the amount of “slack” between the input and output logic gates that allows for voltage changes due to noise. As long as the noise peaks are within the margins, it will not affect the performance of the circuit. It is desirable to have the thickest noise margins possible.

Definition of Noise Margins V IH IL Undefined Region "1" "0" OH OL NM H L Gate Output Gate Input Noise Margin High Noise Margin Low The slide shows the noise margin defined between two gates that are connected together. The noise margin is the amount of “slack” between the input and output logic gates that allows for voltage changes due to noise. As long as the noise peaks are within the margins, it will not affect the performance of the circuit. It is desirable to have the thickest noise margins possible.

The Regenerative Property Large noise margin alone not sufficient for proper operation Gate must “boost” weak levels back to nominal values Known as regeneration (of levels) Non-regenerative gate output will converge to intermediate value Conditions for regeneration: VTC transient region gain >1 (absolute value) Gain in the two legal zones must be < 1 Apart from noise margin. The gate should also be able to kick back a weak signal to the proper level as it goes through a gate. This ability is known as the gate’s regenerative property. In order to be regenerative, a gate must possess a high gain at the transient region. Make sure you understand the conditions for regeneration.

The Regenerative Property A non-regenerative gate will send a weak signal more into the ‘gray’ transition region, as shown above.

Directivity A gate must be unidirectional: input not affected by output changes causes noise in input otherwise Real gate: full directivity never achievable capacitive coupling causes feedback

Fan-in and Fan-out Fan-out: Number of load gates, N, that are connected to the output of the driving gate tends to lower the logic levels deteriorates dynamic performance gate must have low output resistance to drive load library cells have maximum fan-out specification Fan-in: Number of inputs, M, to the gate large fan-in gates are more complex results in inferior static and dynamic performance Large fan-out can be reduced by hierarchical design

Fan-in and Fan-out

The Ideal Gate Static CMOS comes close to ideal V g= -¥ R = ¥ = 0 out in out g= -¥ R i = ¥ o = 0 Noise margins in this gate are maximum Static CMOS comes close to ideal

VTC of Real Inverter 0.0 1.0 2.0 3.0 4.0 5.0 V (V) ( ) NM L t u o M H Poor noise margins, Vm is logic threshold for the device

Dynamic Behavior Propagation Delay, Tp Defines how quickly output is affected by input Measured between 50% transition from input to output tpLH defines delay for output going from low to high tpHL defines delay for output going from high to low Overall delay, tp, defined as the average of tpLH and tpHL

Dynamic Behavior Rise and fall time, Tr and Tf Defines slope of the signal Defined between the 10% and 90% of the signal swing Propagation delay and rise and fall times affected by the fan-out due to larger capacitance loads

Delay Definitions

The Ring Oscillator A standard method is needed to measure the gate delay It is based on the ring oscillator 2Ntp >> tf + tr for proper operation

Ring Oscillator

Power Dissipation Power consumption determines heat dissipation and energy consumption Influence design decisions: packaging and cooling width of supply lines power-supply capacity # of transistors integrated on a single chip Power requirements make high density bipolar ICs impossible (feasibility, cost, reliability)

Power Dissipation Supply-line sizing Battery drain, cooling

Power Dissipation Ppeak = static power + dynamic power Dynamic power: (dis)charging capacitors temporary paths from VDD to VSS proportional to switching frequency Static power: static conductive paths between rails leakage increases with temperature

Power Dissipation Propagation delay is related to power consumption tp determined by speed of charge transfer fast charge transfer => fast gate fast gate => more power consumption Power-delay product (PDP) quality measure for switching device PDP = energy consumed /gate / switching event measured using ring oscillator

Power Dissipation Supply-line sizing Battery drain, cooling Energy consumed /gate /switching event

CMOS Inverter: Steady State Response CMOS technology: No path exists between VDD and VSS in steady state No static power consumption! (ideally) Main reason why CMOS replaced NMOS in early 80’s NMOS technology: Has NMOS pull-up device that is always ON Creates voltage divider when pull-down is ON Power consumption puts upper bound on (# devices / chip)

Static CMOS: Properties VOH = VDD , VOL = VSS (GND) voltage swing equal to supply voltage provides high noise margins Logic levels not dependent on relative device sizes transistors can be minimum size known as ratioless logic (as opposed to ratioed logic based on NMOS devices)

Static CMOS: Properties Finite resistance always exists between output and supply rails (in steady state) low output impedance (typically 10K ohms) less sensitive to noise Extremely high input resistance MOSFET gate perfect insulator and draws no DC current steady-state input current zero (ignoring leakage) can have large fan-out and still be functional fan-out has no effect on steady-state behavior

Voltage Transfer Characteristic

CMOS Inverter Load Characteristics G S D G S

G S PMOS Load Lines D G S V I V = V +V I = - I V I =-5 =-2 V I =0 =3 V out I Dn V in = V DD +V GSp I Dn = - I Dp out DSp V DSp I Dp GSp =-5 =-2 V DSp I Dn in =0 =3 V out I Dn in =0 =3 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp

CMOS Inverter Load Lines PMOS NMOS X 10-4 Vin = 0V Vin = 2.5V Vin = 0.5V Vin = 2.0V IDn (A) Vin = 1.0V Vin = 1V Vin = 1.5V Vin = 1.5V Vin = 2V Vin = 0.5V Vin = 1.5V Vin = 1.0V dc points located at the intersection of the corresponding load lines Note all operating points are located either at the high or low output levels Vin = 2.0V Vin = 0.5V Vin = 2.5V Vin = 0V Vout (V) 0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

G S Cutoff Linear Saturation pMOS nMOS Regions of operations Vin -VDD= VGS> VT Vin -VDD=VGS< VT Vin -Vout=VGD< VT Vin -VDD=VGS> VT Vin -Vout=VGD>VT nMOS Vin = VGS< VT Vin =VGS> VT Vin -Vout =VGD> VT Vin -Vout =VGD< VT Regions of operations For nMOS and pMOS In CMOS inverter G S D G S

CMOS Inverter Load Characteristics For valid dc operating points: current through NMOS = current through PMOS => dc operating points are the intersection of load lines All operating points located at high or low output levels => VTC has narrow transition zone high gain of transistors during switching transistors in saturation high transconductance (gm) high output resistance (voltage controlled current source)

CMOS Inverter VTC Vout (V) Vin (V) NMOS off PMOS res NMOS sat PMOS res PMOS sat Vout (V) NMOS res PMOS sat NMOS res PMOS off For lecture VTC of the inverter exhibits a very narrow transition zone; high gain during switching transient (when both PMOS and NMOS are simultaneously on and in saturation). In that region, a small change in input voltage results in a large output voltage variation. Indicate on VTC plot where VTn and VTp lie Vin (V)

Voltage Transfer Characteristic

VM  rVDD/(1 + r) where r = kpVDSATp/knVDSATn Switching Threshold VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = VGS) VM  rVDD/(1 + r) where r = kpVDSATp/knVDSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want VM = VDD/2 (to have comparable high and low noise margins), so want r  1 (W/L)p kn’VDSATn(VM-VTn-VDSATn/2) (W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2) Assumes: The supply voltage is high enough so that the devices are velocity-saturated (VDSAT < VM – VT) and ignores channel length modulation. Reminder: k = k’W/L and k’ = mu Cox (mu is carrier mobility) Larger r to move VM upwards means making the PMOS wider Smaller r to move VM downwards means making the NMOS wider =

Switch Threshold Example In our generic 0.25 micron CMOS process, using the process parameters from table a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5) VT0(V) (V0.5) VDSAT(V) k’(A/V2) (V-1) NMOS 0.43 0.4 0.63 115 x 10-6 0.06 PMOS -0.4 -1 -30 x 10-6 -0.1 (W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2) (W/L)n -30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2) = x = 3.5 For class goal is to have Vm at Vdd/2 3.5 x 1.5 so (W/L)p = 5.25 (W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V

Simulated Inverter VM VM is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves VM towards VDD Increasing the width of the NMOS moves VM toward GND VM (V) Plot needs work – but it’s the best I could do with powerpoint graphing Small variations in ratio don’t make a lot of difference To move the VM to 1.5V requires a ratio of 11 !!! Note that the x axis is semilog ~3.4 .1 (W/L)p/(W/L)n Note: x-axis is semilog

Noise Margins Determining VIH and VIL By definition, VIH and VIL are where dVout/dVin = -1 (= gain) VOH = VDD NMH = VDD - VIH NML = VIL - GND Approximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/g So high gain in the transition region is very desirable Vout VM A high gain in the transition region is VERY desirable. In the extreme case of an infinite gain, the noise margins simplify to VOH – VM and VM – VOL for NMH (ideally, VDD – VM) and NML (ideally, VM – GND), respectively, and span the complete voltage swing. VOL = GND Vin A piece-wise linear approximation of VTC

CMOS Inverter VTC from Simulation 0.25um, (W/L)p/(W/L)n = 3.4 (W/L)n = 1.5 (min size) VDD = 2.5V VM  1.25V, g = -27.5 VIL = 1.2V, VIH = 1.3V NML = NMH = 1.2 (actual values are VIL = 1.03V, VIH = 1.45V NML = 1.03V & NMH = 1.05V) Output resistance low-output = 2.4k high-output = 3.3k Vout (V) Note: simulation overestimates the gain – as seen on the next slide, the maximum gain (at VM) is only -17 And piece-wise linear approximation model is optimistic wrt noise margins. Low output resistance is a good measure of the sensitivity of the gate wrt noise induced at the output and should be as low as possible. Vin (V)

Gain Determinates Vin gain Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM (1+r) g  ---------------------------------- (VM-VTn-VDSATn/2)(n - p ) Determined by technology parameters, especially channel length modulation (). Only designer influence through supply voltage and VM (transistor sizing).

Impact of Process Variation Good PMOS Bad NMOS Vout (V) Nominal Bad PMOS Good NMOS A good device has a small oxide thickness (-3nm), a small length (-25nm), a higher width (+30nm) and a smaller threshold (-60mV). The opposite is true for a bad device. Vin (V) Pprocess variations (mostly) cause a shift in the switching threshold

Scaling the Supply Voltage Vin (V) Vout (V) Vout (V) Not the best curve for 0.5 supply (but the best I could do in ppt). Observations The gain of the inverter in the transition region increases with a reduction in Vdd. For a fixed r, VM is proportional to Vdd. At a voltage of 0.5V (just 100mV above the threshold of the transistors) the width of the transition region measures only 10% of the supply voltage (and a gain of -35), while it widens to 17% for 2.5V But, reducing the supply Is absolutely detrimental to the performance of the gate The dc characteristics become increasingly sensitive to variations in the device parameters (e.g., VT) Scaling the supply means reduced signal swing making the gate more sensitive to external noise sources that don’t scale Note, in plot on the right, we still obtain an inverter even though the supply voltage is not large enough to turn the transistors on! The subthreshold current is sufficient to switch the gate between low and high levels, as well as to provide enough gain to produce an acceptable VTC. The ultimate show stopper is when the gain in the transition region approaches 1 (as in the green curve on the right plot) – giving the true lower bound on supply scaling (without cooling the chip). Gain=-1 Vin (V) Device threshold voltages are kept (virtually) constant Device threshold voltages are kept (virtually) constant

Propagation Delay

Switch Model of Dynamic Behavior VDD Rn Vout CL Vin = V DD VDD Rp Vout CL Vin = 0 For class. response determined mainly by the output capacitance of the gate, CL - drain diffusion capacitance of the NMOS and PMOS transistors; the connecting wires, and the input capacitances of the fan-out gates A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance or the transistor (or both) Decreasing the on-resistance achieved by increasing the W/L ratio of the device Be award that the on-resistance of the NMOS and PMOS transistors is not constant; rather it is a nonlinear function of the voltage across the transistor Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)

What is the Inverter Driving? DD in out M 1 2 3 4 C db gd 12 w g Fanout Interconnect L Simplified Model

CMOS Inverter Propagation Delay Approach 1

CMOS Inverter Propagation Delay Approach 2

CMOS Inverter: Transient Response How can the designer build a fast gate? tpHL = f(Ron*CL) Keep output capacitance, CL, small low fan-out keep interconnections short (floor-plan your layout!) Decrease on-resistance of transistor increase W/L ratio make good contacts (slight effect)

CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching

MOS Transistor Small Signal Model Define

Determining VIH and VIL VIH and VIL are based on derivative of VTC equal to -1

Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpLH tpHL

Inverter Transient Response VDD=2.5V 0.25m W/Ln = 1.5 W/Lp = 4.5 Reqn= 13 k ( 1.5) Reqp= 31 k ( 4.5) Vin tf tr Vout (V) tpHL tpLH tpHL = 36 psec tpLH = 29 psec so tp = 32.5 psec For lecture Reqn = 8.67 and Reqp = 6.89 The top time is from simulation the bottom from solving the (simplified) equations Note overshoots on simulated output signals. Caused by the gate-drain capacitances of the inverter transistors which couple the steep voltage step at the input node directly to the output before the transistors can even start to react to the changes at the inputs. These overshoots have a negative effect on gate performance and explain why the simulated delays are larger than the estimations. x 10-10 t (sec) From simulation: tpHL = 39.9 psec and tpLH = 31.7 psec

Design for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase VDD (????)

Delay as a function of VDD

Sizing Impacts on Delay x 10-11 for a fixed load The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area). tp(sec) Making S infinitially large yields the maximum obtainable performance gains. Bulk of the improvement is already obtained for S = 5, sizing factors larger than 10 barely yield any extra gain. While sizing up an inverter reduces its delay, it also increase its input capacitance – impacting the delay of the driving gate! self-loading effect (intrinsic capacitance dominates) S

PMOS/NMOS Ratio Effects x 10-11  of 2.4 (= 31 k/13 k) gives symmetrical response  of 1.6 to 1.9 gives optimal performance tpLH tpHL tp tp(sec) Observe that the rising and falling delays are identical at the predicted point of beta of 2.4 (the crossing point of the three curves) that is the preferred operation point when the worst-case delay is the prime concern.  = (W/Lp)/(W/Ln)

Impact of Rise Time on Delay Rise time is a function of fan-in

Inverter Sizing

CMOS Inverter: Four Views Vdd Gnd Vin Vout Logic Transistor Layout Physical

CMOS Inverter Layout Out In metal1-poly via metal1 polysilicon metal2 VDD GND NMOS (2/.24 = 8/1) PMOS (4/.24 = 16/1) metal2 metal1 polysilicon In Out metal1-poly via metal2-metal1 via metal1-diff via pdiff ndiff

Inverter Delay Minimum length devices, L=0.25mm Assume that for WP = 2WN =2W same pull-up and pull-down currents approx. equal resistances RN = RP approx. equal rise tpLH and fall tpHL delays Analyze as an RC network 2W W Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL Load for the next stage:

Inverter with Load RW CL RW tp = k RWCL k is a constant, equal to 0.69 Delay RW CL RW Load (CL) tp = k RWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1

Inverter with Load CP = 2Cunit 2W W Cint CL CN = Cunit Delay 2W W Cint CL Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)

Delay Formula Cint = gCgin with g  1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

Impact of Fanout on Delay Extrinsic capacitance, Cext, is a function of the fanout of the gate - the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both Cg and Cint are proportional to the gate sizing, so Cint = Cg is independent of gate sizing and tp = tp0 (1 + Cext/ Cg) = tp0 (1 + f/) i.e., the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f f = Cext/Cg gamma is close to 1 for most submicron processes.

tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ ) Inverter Chain Real goal is to minimize the delay through an inverter chain the delay of the j-th inverter stage is tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ ) and tp = tp1 + tp2 + . . . + tpN so tp = tp,j = tp0  (1 + Cg,j+1/(Cg,j)) In Out CL Cg,1 1 2 N ingores wiring capacitance for now If CL is given How should the inverters be sized? How many stages are needed to minimize the delay?

Apply to Inverter Chain Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N Minimize the delay, find N - 1 partial derivatives Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 Size of each stage is the geometric mean of two neighbors each stage has the same effective fanout (Cout/Cin) each stage has the same delay

Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay

Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages:

Determining N: Optimal Number of Inverters What is the optimal value for N given F (=fN) ? if the number of stages is too large, the intrinsic delay of the stages becomes dominate if the number of stages is too small, the effective fan-out of each stage becomes dominate N The optimum N is found by differentiating the minimum delay expression divided by the number of stages and setting the result to 0, giving  + F - ( F lnF)/N = 0 For  = 0 (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e = 2.71828 For  = 1 (the typical case) the optimum effective fan-out (tapering factor) turns out to be close to 3.6

Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF

Optimum Effective Fan-Out normalized delay Fopt note that curve on the left starts to increase at 5 ! reinforcing last bullet  f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 (for  = 1) But too many stages has a substantial negative impact on delay

Example of Inverter (Buffer) Staging 1 N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 Cg,1 = 1 CL = 64 Cg,1 8 1 Cg,1 = 1 CL = 64 Cg,1 4 16 1 Cg,1 = 1 CL = 64 Cg,1 2.8 8 22.6 1 Cg,1 = 1 CL = 64 Cg,1

Impact of Buffer Staging for Large CL Unbuffered Two Stage Chain Opt. Inverter Chain 10 11 8.3 100 101 22 16.5 1,000 1001 65 24.8 10,000 10,001 202 33.1 Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads.

Input Signal Rise/Fall Time x 10-11 In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay. tp(sec) tp increases linearly with increasing input slope, ts, once ts > tp ts is due to the limited driving capability of the preceding gate Have assumed until now that the input signal abruptly changes from 0 to Vdd or vice versa. In reality, the input signal changes gradually and, temporarily, the PMOS and NMOS transistors conduct simultaneously). ts is the input switching time (delay) slope If the driving gate were infinitely strong, its output slope would be unaffected (by the load). ts(sec) x 10-11 for a minimum-size inverter with a fan-out of a single gate

tip = tistep +  ti-1step (  0.25) Design Challenge A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs. tip = tistep +  ti-1step (  0.25) Keep signal rise times smaller than or equal to the gate propagation delays. good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering. tstep is for the zero input slope

Delay with Long Interconnects When gates are farther apart, wire capacitance and resistance can no longer be ignored. tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan where Rdr = (Reqn + Reqp)/2 = 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2 cint Vin cfan (rw, cw, L) Vout Have been ignoring wire capacitance and resistance so far. Can use the Elmore delay expression to account for long wire capacitance and resistance. At L = 65 micron, the delay of the interconnect becomes equal to the intrinsic delay caused purely by the device parasitics. The extra delay is solely due to the linear factor in the equation, and more specifically due to the extra capacitance introduced by the wire. The quadratic factor only becomes dominant at much larger wire lengths (> 7 cm) due to the high resistance of the (minimum-size) driver transistor. Wire delay rapidly becomes the dominate factor (due to the quadratic term) in the delay budget for longer wires.

Power Dissipation

Where Does Power Go in CMOS?

Dynamic Power Dissipation Vin Vout C L Vdd Energy/transition = C L * V dd 2 Power = Energy/transition * f = C * f Need to reduce C , V , and f to reduce power. Not a function of transistor sizes!

Modification for Circuits with Reduced Swing

Adiabatic Charging 2 2 2

Adiabatic Charging

Node Transition Activity and Power

Transistor Sizing for Minimum Energy Goal: Minimize Energy of whole circuit Design parameters: f and VDD tp  tpref of circuit with f=1 and VDD =Vref

Transistor Sizing (2) Performance Constraint (g=1) Energy for single Transition

Transistor Sizing (3) VDD=f(f) E/Eref=f(f) F=1 2 5 10 20

Short Circuit Currents

How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so ...

Minimizing Short-Circuit Power Vdd =3.3 Vdd =2.5 Vdd =1.5

Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

Reverse-Biased Diode Leakage JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS JS doubles for every 9 deg C!

Subthreshold Leakage Component

Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance Device Sizing: for F=20 fopt(energy)=3.53, fopt(performance)=4.47

Impact of Technology Scaling

Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower power

Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 2-3 years

Technology Generations

Technology Evolution (2000 data) International Technology Roadmap for Semiconductors 186 177 171 160 130 106 90 Max mP power [W] 1.4 1.2 6-7 1.5-1.8 180 1999 1.7 1.6-1.4 2000 14.9 -3.6 11-3 7.1-2.5 3.5-2 2.1-1.6 Max frequency [GHz],Local-Global 2.5 2.3 2.1 2.4 2.0 Bat. power [W] 10 9-10 9 8 7 Wiring levels 0.3-0.6 0.5-0.6 0.6-0.9 0.9-1.2 1.2-1.5 Supply [V] 30 40 60 Technology node [nm] 2014 2011 2008 2004 2001 Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

Technology Evolution (1999)

ITRS Technology Roadmap Acceleration Continues

Technology Scaling (1) Minimum Feature Size

Number of components per chip Technology Scaling (2) Number of components per chip

Technology Scaling (3) Propagation Delay tp decreases by 13%/year 50% every 5 years! Propagation Delay

Technology Scaling Models

Scaling Relationships for Long Channel Devices

Transistor Scaling (velocity-saturated devices)

Dilbert

Dilbert

Dilbert

Dilbert

Dilbert