1 Logic analyzers Testing and Debugging F Logic Probe - very simple but enough for quick test F Oscilloscope íShows electrical details ç Benefits: Wideband, accurate ç Disadvantages: < 4 inputs; triggering F Logic analyzer íShows 0/1 - according to some threshold ç Benefits: Many channels, trigger on patterns ç Disadvantages: Idealized waveforms, insufficient access F 3. Embedded test íYou design in built-in test features ç Benefits: Only way to test large chips ç Disadvantages: Uses chip area, incomplete scan, difficult design

2 Logic analyzers Logic Probe F Examine one signal íDisplay 0/1/Z/changing íSelect TTL or CMOS technology (5v) F Catch pulses íConnect to signal, set pulse íIf pulse occurs, probe triggers and catches it F Very rudimentary, but quick to catch simple things íUnconnected signals (bad protoboard, broken wire) íWrong connections íBad chips

3 Logic analyzers Oscilloscope F Samples signal voltage over time íDisplays signal as a waveform, one voltage value per time step\ F Triggering íChoose when to start sampling the signals íSlope: rising voltage/falling voltage íThreshold: trigger when signal reaches this value F Repeat mode íAssume that signal is periodic íRepeated triggering captures the same signal íYou’ll never see a glitch F Capture mode íTriggers only once, stores waveform in memory íYou’ll be very lucky to catch a glitch

4 Logic analyzers F Instruments for acquiring digital data íWide data “bus” - capture many signals íMemory stores bus data íSmart triggering decides what data to store íEmbedded computer processes the data F We use the Tektronix TLA704 í128 channels í32k memory per channel í100MHz state í2GSPS sampling íWin95 interface

5 Logic analyzers Logic analyzer physical model F A mainframe íHousing, bus, controller, UI F Plug-in modules íModules acquire data íOurs TLAs have 4 7L1 modules ç 32k memory depth ç 100MHz state ç 32 data and 2 clock each F Probe pods íPods are wire bundles íProbes attach to your circuit ç We have P6417 probes

6 Logic analyzers Probe pods

7 Logic analyzers Logic analyzer conceptual model F All parameters are adjustable íThreshold voltage íClock rate íTrigger conditions íMemory depth

8 Logic analyzers Clocking a logic analyzer F Samples data every clock cycle F External/synchronous clocking íYou supply the clock íUse when you need to see long data records ç Analyzer stores one sample per clock period F Internal/asynchronous clocking íAnalyzer supplies the clock ç 4ns to 50ms íUse when you need to see precise timing ç Find glitches

9 Logic analyzers Triggering and acquisition F Derive trigger from sampled data íData values íData ranges íSignals from another module íInternal counters F Data acquisition is continuous íMemory is a circular buffer íNew samples continually overwrite oldest samples íTrigger tells the acquisition to stop F Triggers can qualify acquisition íStore only selected data

10 Logic analyzers Modules are semi-autonomous F Each module has its own setup íIts own clock íIts own trigger íAcquires and stores its own data F Modules communicate via their trigger programs íCan trigger all modules íOr have one module arm another F All data is time correlated íRegardless of the module

11 Logic analyzers System window F Top-level in hierarchy íOpen other windows ç Module ç Data íCreate new data, listing, and waveform windows íShows which modules are associated with a data window íEnable/disable modules íSave and load files F *Note: We don't have DSO modules

12 Logic analyzers Module setup window F Each module has its own setup and trigger windows íSet up each module independently F Set all parameters íAssign channels to groups íThresholds íClock rate íComparisons F Configure setup before trigger íTrigger settings depend on the module settings

13 Logic analyzers Module trigger window F Triggering is the key feature of a logic analyzer íTells the analyzer how to find the data that you want ç Trigger off a data pattern ç Trigger off a data sequence íMultiple states ç Multiple clauses per state F Analyzer has a trigger library! F Logic analyzers are designed for non-repetitive data íUnlike an oscilloscope

14 Logic analyzers Data windows F Many types íListing window íWaveform window íHistogram window íSource-data window F Features common to all íCursors íFlags íScroll íSearch

15 Logic analyzers Capturing glitches F Trigger on the glitch íTriggering looks for multiple transitions in a clock cycle íCaptures dynamic hazards F Can also trigger on setup and hold violations

16 Logic analyzers Other features: Activity indicator F How do you know if a pod is active? íHooked up properly? íSeeing data?

17 Logic analyzers Other features: Programmability F Symbols íYou define in a LUT íAnalyzer assigns symbols to data patterns F User programs íe.g. export to file and continue

18 Logic analyzers Other features: µP support F Analyzer disassembles data to µP mnemonics F Requires special module podsets

19 Logic analyzers Testing: The big picture F The difference between internal and external BW has driven test technology 1. External test 2. Embedded scan path 3. High-BW embedded 4. Embedded source 5. ??? External BW  (# of I/O) * (external clock rate) Internal BW  (# of transistors)* (internal clock rate) From IEEE Spectrum, 7/99, pgs. 55 / 57

20 Logic analyzers Semiconductor scaling confounds testing F Testing is a key obstacle to future advancement in digital technology F Need to ensure logic functionality íDespite ever-more-limited access to internal logic F Testing at the board, subsystem, and system level becomes ever harder From IEEE Spectrum, 7/99, p. 55

21 Logic analyzers System-on-a-chip testing F IEEE P1500 standard íFor embedded core test íIn development F Standardized core test language F Standardized core test wrapper íConfigurable íScalable From IEEE Spectrum, 7/99, p. 59