Welcome to CSE 143! Microelectronic System Design Spring 2009 Instructor: Rajesh K. Gupta, rgupta@ucsd.edu

Welcome! Course Objective: Course Orientation: You will not learn: Provide an introduction to microelectronic system design Course Orientation: a systems view of the design and design process, not components system engineering issues related to performance, quality automation-centric design: tools and methodologies. You will not learn: microelectronic device design, physics, process technology circuit, logic modeling, design, synthesis, simulation computer architecture CAD algorithms, writing CAD tools. You should get skills in HDL-based circuit, system modeling, synthesis, optimization.

Course Organization There are three basic parts to the course Review of microelectronics, circuits, process technology Structured VLSI design: design styles and global issues HDL-based modeling, synthesis and optimization Not necessarily covered in that order Course logistics described on the class web-page: http://mesl.ucsd.edu/gupta/cse143.html Section ID: 656577 Lectures: Tu/Th 5-6:30PM CENTER 217A Office Hours: Wed 2-4, call or drop by (822-4391, CSE 2120)

Lectures Welcome, Introduction to Microelectronic Circuits and Systems (Thursday, March April 2, 2009) Review of Microelectronic Processing and Devices Circuit Styles, Structured VLSI Design Clocking Microsystem Modeling using HDLs Simulation versus Synthesis using VHDL From Modeling to Circuit Synthesis: Global Issues Design for Low Power Architectural Designs Design Verification Design for Test

Questions?

Three Trends Driving Microelectronic Systems Design Trend 1: Relentless Digitization of Signals and Systems

Microelectronic System Trends -- 2 Trend 2: increasing use of “embedded intelligence” variety of (multiple) compute engines available on-chip Graphics Controller Cellphone Baseband

Microelectronic System Trends -- 3 Trend 3: Networking of embedded intelligence multiple comm. front-ends, networking available on-chip The consequence: smart “spaces”, intelligent interfaces, sensor networks Integrated circuit chips are driving tremendous capability increases

Source: Mani Srivastava, UCLA Pentium 3 & Pentium 4 28.1M transistors 106 mm^2 die size 0.18 micron, 6-layer metal CMOS 42M transistors 217 mm^2 die 0.18-micron process 2GHz clock Source: Mani Srivastava, UCLA

Microprocessors Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."

Moore’s Law Defines The Competitive Necessity

The ITRS: Tao of Scaling http://public.itrs.net Source: Ken Yang, UCLA

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT Vout Vin DEVICE n+ S D G Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."

Design Process Conceptualization: function & structure HLM, behavioral modeling Architecture: structure and organization microarchitectural implementation Logical implementation: gates, modules logic synthesis, logic verification, static timing analysis Circuit implementation: transistors circuit simulations Physical design, verification floorplanning, placement, routing, dynamic timing analysis

Many Implementation Choices Speed Power Cost Microprocessors Domain-specific processors DSP Network processors Microcontrollers ASIPs Reconfigurable SoC FPGA Gate-array ASIC High Low Volume

E.g. Degree of Customization of Processor Architecture The architecture of the computation engine used to implement desired functionality Processor does not have to be programmable “Processor” not equal to general-purpose processor total = 0 for i = 1 to N loop total += M[i] end loop Application-specific Registers Custom ALU Datapath Controller Program memory Assembly code for: total = 0 for i =1 to … Control logic and State register Data memory IR PC Single-purpose (“hardware”) Control logic State register index total + Register file General logic and State register General-purpose (“software”) [Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]

General-purpose Microprocessors Programmable device used in a variety of applications Also known as “microprocessor” Features Program memory General datapath with large register file and general ALU User benefits Low time-to-market and NRE costs High flexibility “Pentium” the most well-known, but there are hundreds of others IR PC Register file General ALU Datapath Controller Program memory Assembly code for: total = 0 for i =1 to … Control logic and State register Data memory [Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]

Application-specific Instruction Processors, ASIP Programmable processor optimized for a particular class of applications having common characteristics Compromise between general-purpose and single-purpose processors Features Program memory Optimized datapath Special functional units Benefits Some flexibility, good performance, size and power Controller Datapath Control logic and State register Registers Custom ALU IR PC Data memory Program memory Assembly code for: total = 0 for i =1 to … [Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]

Single-purpose ‘Processors,’ or ASIC Digital circuit designed to execute exactly one program a.k.a. coprocessor, accelerator or peripheral Features Contains only the components needed to execute a single program No program memory Benefits Fast Low power Small size Datapath Controller Control logic State register Data memory index total + [Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]

E.g. ASIC ASIC Features Area: 4.6 mm x 5.1 mm Speed: 20 MHz @ 10 Mcps Technology: HP 0.5 mm Power: 16 mW - 120 mW (mode dependent) @ 20 MHz, 3.3 V Avg. Acquisition Time: 10 ms to 300 ms A direct sequence spread spectrum (DSSS) radio receiver ASIC (UCLA)

The Implementation Choice is Important

The Co-design Ladder In the past: Hardware/software “codesign” Hardware and software design technologies were very different Recent maturation of synthesis enables a unified view of hardware and software Hardware/software “codesign” Implementation Assembly instructions Machine instructions Register transfers Compilers (1960's,1970's) Assemblers, linkers (1950's, 1960's) Behavioral synthesis (1990's) RT synthesis (1980's, 1990's) Logic synthesis (1970's, 1980's) Microprocessor plus program bits: “software” VLSI, ASIC, or PLD implementation: “hardware” Logic gates Logic equations / FSM's Sequential program code (e.g., C, VHDL) The choice of hardware versus software for a particular function is simply a tradeoff among various design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no fundamental difference between what hardware or software can implement. [Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]

Core-based Design: System on Chip SC3001 DIRAC chip (a radio receiver) from Sirius Communications

Reconfigurable SoC Triscend’s A7 CSoC Other Examples Atmel’s FPSLIC (AVR + FPGA) Altera’s Nios (configurable RISC on a PLD) Triscend’s A7 CSoC

IP-based Design [Vincentelli]

Map from Behavior to Architecture [Vincentelli]

Summary: Microsystems in New “Spaces” Instrumented wide-area spaces Personal area spaces Internet end-points In-body, in-cell, in-vitro spaces Generational shift in computing devices lot more of everything: computing, networking, communications lot less of power, energy, volume, weight, patience Application is everything, the possibilities are limitless System architectures are due for an overhaul the architectures are (radically) changed/challenged the programming context is changed the system software contract is changed new awareness: location, power, timing, reactivity, stability Next Lecture: Overview of Semiconductor Devices/Processes.