SNS Integrated Control System SNS Timing Master LA-UR-03-3377 Eric Bjorklund.

Slides:



Advertisements
Similar presentations
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.
Advertisements

XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
System Integration and Performance
INPUT-OUTPUT ORGANIZATION
01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.
Stephanie Allison LCLS Event System 14 June LCLS Event System Outline HW Block Diagram Timing Requirements Time Lines EVG.
ESS Timing System Plans and Requirements Timo Korhonen Chief Engineer, Integrated Control System Division May 19, 2014.
Wir schaffen Wissen – heute für morgen Babak Kalantari, PSI MRF workshop, Prague, Eli Beamlines Paul Scherrer Institut SwissFEL Timing System.
Dale E. Gary Professor, Physics, Center for Solar-Terrestrial Research New Jersey Institute of Technology 1 3/15/2012OVSA Preliminary Design Review Meeting.
Dale E. Gary Professor, Physics, Center for Solar-Terrestrial Research New Jersey Institute of Technology 1 11/7/2011OVSA Technical Design Meeting.
A SINGLE FREQUENCY GPS SOFTWARE RECEIVER
Wireless Motion Capture Mid-Year Design Review Seth Berkowitz Dean Howarth Eric Marklein Ashesh Rastogi Advisor: Professor Daniel Schaubert.
SNS Integrated Control System SNS Machine Protection System EPICS Workshop April 27, 2005 Coles Sibley.
1 ECE 263 Embedded System Design Lessons 2, 3 68HC12 Hardware Overview, Subsystems, and memory System.
Dayle Kotturi SLC April 29, 2004 Outline Motivation Key Components Status Update SLC / EPICS Timing Software Tasks Hardware.
Range Measurement Unit Messenger Mercury Laser Altimeter Basic Familiarization.
INPUT-OUTPUT ORGANIZATION
The TIMING System … …as used in the PS accelerators.
3/7/05A. Semenov Batch-by-Batch Intensity Monitor 1 Two-Channel Batch by Batch Intensity Monitor for Main Injector BBI.
AWAKE RF Synchronization and LLRF Budget Review Reported by Wolfgang Hofle Acknowledgement: A. Butterworth, H. Damerau, S. Doebbert, J. Molendijk, S. Rey.
SNS Integrated Control System EPICS Collaboration Meeting SNS Machine Protection System SNS Timing System Coles Sibley xxxx/vlb.
ICS – Software Engineering Group 1 The SNS General Time Timestamp Driver Sheng Peng & David Thompson.
LHC Beam Dump System Technical Audit Trigger Synchronisation Unit.
INTRODUCE OF SINAP TIMING SYSTEM
ORNL/SNS Spallation Neutron Source Low-Level RF Control System Kay-Uwe Kasemir, Mark Champion April 2005 EPICS Meeting 2005, SLAC.
CRIO as a hardware platform for Machine Protection. W. Blokland S. Zhukov.
Distribution of machine parameters over GMT in the PS, SPS and future machines J. Serrano, AB-CO-HT TC 6 December 2006.
Virtual Accelerator at J-PARC 3 GeV Rapid Cycling Synchrotron H. Harada*, K. Shigaki (Hiroshima University in Japan), H. Hotchi, F. Noda, H. Sako, H. Suzuki,
LANSCE Timing Requirements LA-UR Eric Bjorklund.
Micro-Research Finland Oy Timing System Modules Jukka Pietarinen EPICS Collaboration Meeting, Argonne, June 2006.
NPDGamma: Data Acquisition System October 15th, 2010 NPDGamma Collaboration Meeting ORNL.
RF voltage and frequency interlocks A. Butterworth MP review 17/6/2010.
Advanced Microprocessor1 I/O Interface Programmable Interval Timer: 8254 Three independent 16-bit programmable counters (timers). Each capable in counting.
MRF & Cosylab on timing system: integration support Joze Dedic the best people make cosylab … Head of Hardware.
General Time Update David Thompson Epics Collaboration Meeting June 14, 2006.
1 Timo Korhonen PSI 1. Concepts revisited…again 3. New (Diamond) cards features and status 4. EPICS interface 5. Conclusions SLS & Diamond Timing System.
EUDRB: the data reduction board of the EUDET pixel telescope Lorenzo Chiarelli, Angelo Cotta Ramusino, Livio Piemontese, Davide Spazian Università & INFN.
The CERN LHC central timing A vertical slice Pablo Alvarez Jean-Claude Bau Stephane Deghaye Ioan Kozsar Julian Lewis Javier Serrano.
Timing Distribution System (TDS) 9 April, 2010 Greg Deuerling Rick Kwarciany Neal Wilcer.
SNS Integrated Control System Timing Clients at SNS DH Thompson Epics Spring 2003.
Rome 4 Sep 04. Status of the Readout Electronics for the HMPID ALICE Jose C. DA SILVA ALICE.
Real-time Acquisition and Processing of Data from the GMRT Pulsar Back- ends Ramchandra M. Dabade (VNIT, Nagpur) Guided By, Yashwant Gupta.
Issues in Accelerator Control Bob Dalesio, December 23, 2002.
Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.
Timing Requirements for Spallation Neutron Sources Timing system clock synchronized to the storage ring’s revolution frequency. –LANSCE: MHz.
NUCLOTRON CONTROL SYSTEM (NCS) V.Andreev, E.Frolov, A.Kirichenko, A.Kovalenko, B.Vasilishin, V.Volkov Laboratory of High Energies, JINR, Dubna.
1 LTC Timing AB/CO/HT Central timing hardware layout Telegrams and events Postmortem, XPOC LHC Central Timing API Fill the LHC Use Case Julian Lewis.
The CERN LHC central timing A vertical slice Pablo Alvarez Jean-Claude Bau Stephane Deghaye Ioan Kozsar Julian Lewis Javier Serrano.
Fast Fault Finder A Machine Protection Component.
New PSB Beam Control Upgrade of daughter cards Alfred Blas PSB rf Working group meeting 24/03/ Generation of REV clocks 2.Synchronization with.
LANSCE Master Pattern Generator Eric Björklund LANSCE-8 Controls Software (LA-UR )
Timing System of the Swiss Light Source Timo Korhonen Paul Scherrer Institute, Switzerland 1. Introduction 2. Components and technology 3. SLS Timing Application.
REDNet - Status overview Rok Stefanic Ziga Kroflic
ICALEPCS 2005 Geneva, Oct. 12 The ALMA Telescope Control SystemA. Farris The ALMA Telescope Control System Allen Farris Ralph Marson Jeff Kern National.
BIC Issues Alan Fisher PEP-II Run-4 Post-Mortem Workshop 2004 August 4–5.
BEPC II TIMING SYSTEM EPICS Seminar Presented by Ma zhenhan IHEP 20.August 2002.
ESS Timing System Prototype 2012 Miha Reščič, ICS
Time Management.  Time management is concerned with OS facilities and services which measure real time.  These services include:  Keeping track of.
B2B Transfer System for FAIR (Conceptual Design [1]) Presenter: Jiaoni Bai Professor: Oliver Kester Supervisor: David Ondreka, Dietrich Beck.
Page Beam Instrumentation mini- workshop Conclusions from the Hardware, Timing and MPS mini-workshop Lund, Miha Reščič Deputy Head of
ORNL is managed by UT-Battelle for the US Department of Energy Low Level RF Status and Development Activities at the Spallation Neutron Source Mark Crofford.
ESS Timing System Plans Timo Korhonen Chief Engineer, Integrated Control System Division Nov.27, 2014.
RF acceleration and transverse damper systems
LHC General Machine Timing (GMT)
MICE AFEIIt Timing and Triggering
Beam Sync Output - fiber, one microsecond pulse of Beam Sync Input
SNS Timing System EPICS Workshop April 28, 2005 Coles Sibley
Combiner functionalities
Presentation transcript:

SNS Integrated Control System SNS Timing Master LA-UR Eric Bjorklund

SNS Integrated Control System Basic Characteristics l Event System. –256 events possible. 25 events currently in use. l ~5 millisecond machine cycle. 60 Hz. –Option to go to 120 Hz. when second target added. l 10 second super-cycle. l Clock synchronized with ring RF. –Ring RF is Mz at 1 GeV –Clock is 32 X Ring RF

SNS Integrated Control System Timing System Components Ring RF Timing Reference Generator Neutron Choppers AC Line SNS Event Link Master X32 PLL (33 MHz) SNS Real Time Data Link Master 10 MHz Crystal Osc. Timing Slave (V124S) Machine Protection System ICS IOC's SNS Utility Module LEBT Chopper *4 PLL (64 MHz) Experimental Halls Diagnostics RTDL Event Link Master Timing IOC SNS Time Stamps Beam data RF Gates Extraction Kickers TxHV Gates High resolution timestamps Machine Modes SNS Timestamps Remote Reset Synchronous ISR’s Beam Delay Beam Phase Micro pulse width Macro pulse width SNS Time stamps Delays Gates Triggers Timing System Hardware Timing System UsersExperimental Systems Subsystem Hardware

SNS Integrated Control System Two Transmission Links l Event Link –Transmits the timing events that define a machine cycle. –Each event is 8 bits plus parity (256 events maximum). –Clock is variable and derived from the ring revolution frequency (32 * F rev ). –Events 0 – 63 are generated by the timing system hardware. –Events 64 – 255 are generated by software (no fixed times). l Real-Time Data Link (RTDL) –Transmits machine parameters and data prior to every new cycle. –128 frames possible (expandable to 255). –Each frame contains an 8-bit frame number, 24-bits of data, and an 8-bit CRC. –Clock is 10 MHz.

SNS Integrated Control System Sample RTDL Data Frames Frame NumberData 1 – 3 Time of day 4 Event link period 5 MPS mode 6 60 Hz phase error 7Beam Width 15 IOC Reset Address 17 Pulse Flavor 18-21RF Gate Widths 24 Previous Pulse Status 25 Cycle bit CRC (calculated)

SNS Integrated Control System Timing Master Crate Layout ProcessorUtility ModuleEvent Link Master (V123S)Event Link Input Module (V101S) Line Synch Module (Reserved)Trigger Module (V124S) Frequency CounterEvent MonitorVME Bridge VME BridgeUtility ModuleRTDL Input Module (V206S) (Reserved)RTDL Input Module (V206S) GPS Interface RTDL Input Module (V206S)RTDL Master (V105S)

SNS Integrated Control System Event Link Generator Hardware l Event Link Master Module (V123S) –VME Module. –Generates event link carrier (~17 Mhz). –Accepts, prioritizes, and transmits “hardware” and “software” events. l Event Link Input Module (V101S) –VME Module for generating “hardware” events. –Communicates with the event link master module over the VME P2 backplane. –Hardware events generated from TTL inputs to the V101S –16 events per module.

SNS Integrated Control System RTDL Generator Hardware l RTDL Master Module (V105S) –VME Module –Generates the 10 MHz RTDL Carrier Signal and the RTDL frames. l RTDL Input Module (V206S) –VME Module. 8 frames per module. –Stores the data frames to be sent each cycle on the RTDL. –Communicates with the RTDL master module over the VME P2 backplane.

SNS Integrated Control System Additional Modules l Timing Reference Generator –Double-Wide VME module. –Provides the 60 Hz “Cycle-Start” signal to the event link master module (V123S). –Uses a PLL to track the AC line zero-crossing and “smooth out” power grid frequency fluctuations. –Resolves the “conflict of interest” between power supplies that need to be “line locked” and the neutron choppers’ need for stable timing. l Frequency Counter –VME Module in the Timing Master crate. –Used to monitor the frequency of the event link clock. –Frequency is broadcast on the RTDL and sent to the timing reference generator to compensate for changes in the ring revolution frequency.

SNS Integrated Control System Additional Modules l GPS and GPS Interface Module –GPS provides time source and NTP time service to the site computers. –VME interface card captures the GPS time at each “Cycle Start” time. –Captured time is sent out on the RTDL. l Event Link Monitor –Monitors the event link and records which events occurred and when. –Buffers one full “Super-Cycle” (10 seconds). –Used by the event-link part of the time line monitor to make sure the event link is correct.

SNS Integrated Control System Real-Time Data Link (RTDL) Extract MPS FPAR Event Link End Injection Machine Cycle Timeline 02 ms 1 ms 6 ms4 ms 7 ms 5 ms 8 ms3 ms Anytime Informational Events, non critical timingTime Critical Events, (soft events disabled) RTDL Transmit Snapshot, 1Hz, 6Hz, etc… RTDL Valid RTDL parameter transmission (for next cycle) RF & High Voltage Events MPS FPL System xxx Trigger Events (Alternate) Cycle Start Machine +60 Hz Zero Crossing -60 Hz Zero Crossing Line-Synch Reference Clock Beam On Cycle Start Mostly Stable Triggers Beam On Range Allowed Range for Variable Triggers Extraction Kicker Charge beam accumulation

SNS Integrated Control System The Product and the Perpetrators