ECE 447 Fall 2009 Lecture 10: TI MSP430 Timers and Capture Modes

Timer_A Overview Timer Block –The core, based on 16-bit register TAR –Can chose sources for clock and freq division –Timer block has no output –Flag TAIFG is raised when counter returns to 0 Capture/compare channels –Capture an input, record value in TAR triggered by TACCRn –Compare TAR with the value stored in TACCRn –Request an Interrupt by setting its flag TACCRn CCFIG –Sample an input at a compare event

ECE 447: MSP430 Timer_A System 1.Generating delays - imposing a specific delay between two points in the program by polling. label 1 label2 instr1 instr2 instrN delay

ECE 447: MSP430 Timer_A System 2. Input capture - measuring the time between signal edges 3. Output compare - generating signals with the given timing characteristics start stop startstop pulse width single pulseperiodical signal period

ECE 447: MSP430 Timer_A System 4. Real Time Clock– Produce a periodic signal for the MSP430. period The Real Time Clock Interrupt implements a hardware based time of day clock that can be used by the software.

ECE447: MSP430 Timer I/O Pins and Channels

ECE447: MSP430 Compare/Capture Block Diagram.

MSP430xx4xx Implementation of Timer_A

Timer_A Interrupt Schematic

Timer_A MSP430xx4xx Registers

TACTL: Timer_A Control Register

TAR: Timer_A Register

TACCRx: Timer_A Capture/Compare Register

TACCTLx: Capture/Compare Control Register

TAIV: Timer_A Interrupt Vector Register

ECE447: MPS430 Timer_A input clocks and dividers

ECE447: Measuring Pulse Widths Timer overflows 100  s < width < Configured Period (previous table) width  100  s width  Configured Period (previous table) start stop start stop start stop

ECE 447: Measuring intervals <2 16 clock cycles start 0 FFFF stop

ECE 447: Measuring intervals <2 16 clock cycles (overflow) start 0 FFFF 12 stop

ECE 447: Measuring intervals >2 16 clock cycles start stop 0 FFFF 12 N=3 R

ECE 447: Measuring intervals >2 16 clock cycles start stop 0 FFFF 12 3 R2 R1 N=4 R1+R2=R