9.2 Pipelining Suppose we want to perform the combined multiply and add operations with a stream of numbers: A i * B i + C i for i =1,2,3,…,7

9.2 Pipelining The suboperations performed in each segment of the pipeline are as follows: R1  A i, R2  B i R3  R1 * R2 R4  C i R5  R3 + R4

Pipeline Performance n: instructions k : stages in pipeline  : clockcycle T k : total time n is equivalent to number of loads in the laundry example k is the stages (washing, drying and folding. Clock cycle is the slowest task time n k

Pipelining: Laundry Example Small laundry has one washer, one dryer and one operator, it takes 90 minutes to finish one load: Washer takes 30 minutes Dryer takes 40 minutes “operator folding” takes 20 minutes ABCD

Sequential Laundry This operator scheduled his loads to be delivered to the laundry every 90 minutes which is the time required to finish one load. In other words he will not start a new task unless he is already done with the previous task The process is sequential. Sequential laundry takes 6 hours for 4 loads ABCD PM Midnight TaskOrderTaskOrder Time 90 min

Efficiently scheduled laundry: Pipelined Laundry Operator start work ASAP Another operator asks for the delivery of loads to the laundry every 40 minutes!?. Pipelined laundry takes 3.5 hours for 4 loads ABCD 6 PM Midnight TaskOrderTaskOrder Time

Pipelining Facts Multiple tasks operating simultaneously Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Potential speedup = Number of pipe stages Unbalanced lengths of pipe stages reduces speedup Time to “fill” pipeline and time to “drain” it reduces speedup ABCD 6 PM 789 TaskOrderTaskOrder Time The washer waits for the dryer for 10 minutes

Some definitions Pipeline: is an implementation technique where multiple instructions are overlapped in execution. Pipeline stage: The computer pipeline is to divided instruction processing into stages. Each stage completes a part of an instruction and loads a new part in parallel. The stages are connected one to the next to form a pipe - instructions enter at one end, progress through the stages, and exit at the other end.

Throughput of the instruction pipeline is determined by how often an instruction exits the pipeline. Pipelining does not decrease the time for individual instruction execution. Instead, it increases instruction throughput. Machine cycle. The time required to move an instruction one step further in the pipeline. The length of the machine cycle is determined by the time required for the slowest pipe stage. Some definitions

Instruction pipeline versus sequential processing sequential processing Instruction pipeline

Instruction pipeline (Contd.) sequential processing is faster for few instructions

Two Stage Instruction Pipeline

Difficulties... If a complicated memory access occurs in stage 1, stage 2 will be delayed and the rest of the pipe is stalled. If there is a branch, if.. and jump, then some of the instructions that have already entered the pipeline should not be processed. We need to deal with these difficulties to keep the pipeline moving

5-Stage Pipelining Fetch Instruction (FI) Fetch Operand (FO) Decode Instruction (DI) Write Operand (WO) Execution Instruction (EI) S3S3 S4S4 S1S1 S2S2 S5S S1S1 S2S2 S5S5 S3S3 S4S Time

Five Stage Instruction Pipeline Fetch instruction Decode instruction Fetch operands Execute instructions Write result

6-Stage Pipelining Instruction Fetch Decode Execution Fetch Operand S3S3 S4S4 S1S1 S2S2 S5S S1S1 S2S2 S5S5 S3S3 S4S Time 6 Write operand Calculate operand S6S6

Six Stage Instruction Pipeline Fetch instruction Decode instruction Calculate operands (Find effective address) Fetch operands Execute instructions Write result

Flow chart for four segment pipeline

Two major difficulties Branch Difficulties Data Dependency

Prefetch target instruction Prefetch the target instruction in addition to the instruction following th branch If the branch condition is successful, the pipeline continues from the branch target instruction

Branch target buffer (BTB) BTB is an associative memory Each entry in the BTB consists of the address of a previously executed branch instruction and the target instruction for the branch

Branch Prediction A pipeline with branch prediction uses some additional logic to guess the outcome of a conditional branch instruction before it is executed

Delayed Branch In this procedure, the compiler detects the branch instruction and rearrange the machine language code sequence by inserting useful instructions that keep the pipeline operating without interrupts An example of delay branch is presented in the next section