Design Verification VHDL ET062G & ET063G Lecture 5 Najeem Lawal 2012

DESIGN VERIFICATION 2 OUTLINE –Test Bench –Clock generation –Reading BMP –Generating Control Signal –Testing the result VHDL ET062G & ET063G Lecture 5 Najeem Lawal, 2012

ERROR MANAGEMENT IN VHDL 3 VHDL ET062G & ET063G Lecture 5 Assert statement Syntax: Assert Report Severity ; Message and Error Level are displayed in the simulator console as text. Assert statements can be both sequential and concurrent statements. Assert statements should only be in the test-benches because there are not synthesizable. Najeem Lawal, 2012

ERROR MANAGEMENT IN VHDL 4 VHDL ET062G & ET063G Lecture 5 Entity assert_ex is port ( a,b : in std_logic; q : out std_logic); end entity assert_ex; architecture ex of assert_ex is Najeem Lawal, 2012 architecture ex of assert_ex is begin assert a /= '1' or b /= '1' report “a='1' and b='1' at the same time!” severity Warning; P1 : process(a,b)‏ begin if a ='1' and b = '1' then assert false report “a='1' and b='1'”; end if end process P1; end architecture ex;

TESTBENCHES IN VHDL 5 VHDL ET062G & ET063G Lecture 5 AT LEAST 3 ESSENTIAL COMPONENTS –Unit Under Test UUT –Stimuli generator –Response tester Najeem Lawal, 2012

TESTBENCHES IN VHDL 6 VHDL ET062G & ET063G Lecture 5 AT LEAST 3 ESSENTIAL COMPONENTS –Unit Under Test UUT Your designs 4 bit adder Counter Sliding window Range sensor Edge detector Complete project –Stimuli generator –Response tester Najeem Lawal, 2012

TESTBENCHES IN VHDL 7 VHDL ET062G & ET063G Lecture 5 AT LEAST 3 ESSENTIAL COMPONENTS –Unit Under Test UUT –Stimuli generator Many specialised stimuli generator Clocks, reset Control signals Data signals Models of sensors and actuator your UUT connects to –Response tester Najeem Lawal, 2012

TESTBENCHES IN VHDL 8 VHDL ET062G & ET063G Lecture 5 AT LEAST 3 ESSENTIAL COMPONENTS –Unit Under Test UUT –Stimuli generator –Response tester Many specialised test modules Truth table Established values or controls status Waveform analysis Najeem Lawal, 2012

TYPICAL TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_Project_2010 IS -- nothing here -- no ports -- this is the envelop of the universe END entity test_Project_2010; Closed entity - no port It is the highest module

EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 5 ARCHITECTURE behavior OF test_Project_2010 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT edge_sobel_wrapper PORT( clk : IN std_logic; fsync_in : IN std_logic; rsync_in : IN std_logic; pdata_in : IN std_logic_vector(7 downto 0); fsync_out : OUT std_logic; rsync_out : OUT std_logic; pdata_out : OUT std_logic_vector(7 downto 0) ); END COMPONENT; SIGNAL clk : std_logic := '0'; SIGNAL fsync_in : std_logic := '0'; SIGNAL rsync_in : std_logic := '0'; SIGNAL pdata_in : std_logic_vector(7 downto 0) := (others=>'0'); …..

EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 5 BEGIN -- Instantiate the Unit Under Test (UUT) uut: edge_sobel_wrapper PORT MAP( clk => clk, fsync_in => fsync_in, rsync_in => rsync_in, pdata_in => pdata_in, fsync_out => fsync_out, rsync_out => rsync_out, pdata_out => pdata_out ); img_read : entity work.img_testbench port map ( pclk_i => clk, reset_i => reset, fsync_i => fsync_out, rsync_i => rsync_out, pdata_i => pdata_out, cols_o => open, rows_o => open, col_o => open, row_o => open, fsync_o => fsync_in, rsync_o => rsync_in, pdata_o => pdata_in); Input clock, data & controls And output It’s good to have naming convention Mimics a camera Mimics a monitor Similar clock as UUT To perform some asynchronous functions

EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 5 clock_generate: process (clk) constant T_pw : time := 50 ns; -- Clock period is 100ns. begin -- process img if clk = '0' then clk <= '1' after T_pw, '0' after 2*T_pw; end if; end process clock_generate; reset <= '1', '0' after 60 ns; END; 10 MHz clock. Because the camera is 10 MHz 50 % duty Default value of clock is ‘0’ Clock is just a signal that toggles between ‘0’ and ‘1’ at a predefined rate. Time long enough to do a few house cleaning and data initialization

HINTS Najeem Lawal, VHDL ET062G & ET063G Lecture 5 The UUT IS SELF SUFFICIENT AND SYNTHESISABLE IT CONNECTS TO OTHER DEVICES THROUGH THE FPGA IO PINS CONTAINTS ALL PORTS AND GENERICS FOR IMPLEMENTATION CLOCKS SHOULD BE CLOSE TO FINAL IMPLEMENTATION TIMING REQUIREMENTS YES, WE NEED RESET TO KICK START US FROM OR BRING US TO KNOW STATES

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use std.textio.all; entity img_testbench is port ( pclk_i: in std_logic; reset_i: in std_logic; fsync_i: in std_logic; rsync_i: in std_logic; pdata_i: in std_logic_vector(7 downto 0); cols_o: out std_logic_vector(15 downto 0); rows_o: out std_logic_vector(15 downto 0); col_o: out std_logic_vector(15 downto 0); row_o: out std_logic_vector(15 downto 0); rsync_o: out std_logic; fsync_o: out std_logic; pdata_o: out std_logic_vector(7 downto 0) ); end img_testbench;

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... architecture main of img_testbench is type ByteT is (c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18, c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31,c32,c33,c34, --- subtype Byte is ByteT; type ByteFileType is file of Byte; file infile: ByteFileType open read_mode is "test.bmp"; file outfile: ByteFileType open write_mode is "result_08bits.bmp"; … How to read image files a stream of 8 bit A new type that can read 8-bit character from file.

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture integer to bit_vector conversion function int2bit_vec(A: integer; SIZE: integer) return BIT_VECTOR is variable RESULT: BIT_VECTOR(SIZE-1 DOWNTO 0); variable TMP: integer; begin TMP := A; for i in 0 to SIZE - 1 loop if TMP mod 2 = 1 then RESULT(i) := '1'; else RESULT(i) := '0'; end if; TMP := TMP / 2; end loop; return RESULT; end; … A function that converts integers to bits vector of a given size. Subprograms in VHDL - procedure? - function?

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... begin -- main img_read : process (pclk_i) variable pixelB : Byte; variable pixelG : Byte; variable pixelR : Byte; variable pixel : Byte; variable pixel1 : REAL; variable cols: std_logic_vector(15 downto 0); variable rows: std_logic_vector(15 downto 0); variable col: std_logic_vector(15 downto 0); variable row: std_logic_vector(15 downto 0); variable cnt: integer; variable rsync: std_logic := '0'; variable stop: std_logic; begin -- process img_read if (reset_i = '1') then pdata_o '0'); col:= (others => '0'); row:=(others => '0'); … Store RGB pixel values For reading from the BMP File How many rows, columns which row and column are we in the image file Effective pixel value Counter for blanking Valid pixel indicator When to stop

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... for i in 0 to 53 loop -- read header infos read(infile, pixel); write(outfile, pixel); case i is when 18 =>-- 1st byte of cols cols(7 downto 0 ) := To_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8)); when 19 =>-- 2nd byte of cols cols(15 downto 8) := To_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8)); when 22 =>-- 1st byte of rows rows(7 downto 0 ) := To_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8)); when 23 =>-- 2nd byte of rows rows(15 downto 8) := to_Stdlogicvector(int2bit_vec(ByteT'pos(pixel), 8)); when 24 =>-- do important things cols_o<= cols; rows_o<= rows; cols:= cols - 1; rows:= rows - 1; when others => null; end case; end loop; -- i … Assign output Assign upper limit of internal counters

BMP FILE FORMAT Najeem Lawal, VHDL ET062G & ET063G Lecture 5

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... rsync := '1'; cnt:= 10; stop:= '0'; elsif (pclk_i'event and pclk_i = '1') then rsync_o <= rsync; if rsync = '1' then if row = " " and col = " " then fsync_o <= '1'; else fsync_o <= '0'; end if; …

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... if stop = '0' then read(infile, pixelB); -- B read(infile, pixelG); -- G read(infile, pixelR); -- R pixel1:= (ByteT'pos(pixelB)*0.11) + (ByteT'pos(pixelR)*0.3) + (ByteT'pos(pixelG)*0.59); pdata_o<= CONV_STD_LOGIC_VECTOR(INTEGER(pixel1), 8); col_o<= col; row_o<= row; end if; …

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... if col = cols then col:= (others => '0'); rsync:= '0'; if row = rows then File_Close(infile); stop := '1'; else row := row + 1; end if;-- row else col := col + 1; end if;-- col … Where are we in the image rsync = ‘1’ rsync = ‘0’ rsync = ‘1’ 640 clk 10 clk

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... else-- rsync if cnt > 0 then cnt:= cnt -1; else cnt:= 10; rsync := '1'; end if; pdata_o 'X'); end if;-- rsync …

IMG_TESTBENCH Najeem Lawal, VHDL ET062G & ET063G Lecture 5... if rsync_i = '1' then write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(pdata_i)))); --, pixel); end if; -- rsync_i end if; -- clk end process img_read; end main; …

RANGE SENSOR Najeem Lawal, VHDL ET062G & ET063G SRF –10us pulse to the Trigger input –50ms period between each Trigger pulse –Mode 1 recommended

PROJECT IMPLEMENTATION Najeem Lawal, VHDL ET062G & ET063G CONTROLLER IS FPGA –System Clock and Exposure are generated –Understand timing diagrams and implement the project.

SLIDING WINDOW Najeem Lawal, VHDL ET062G & ET063G –An image is read from left to right and top to bottom sliding –Given an algorithm with many tasks O(x,y) = F(x,y) x I(x,y) –Some of the task are neighbourhood oriented sliding window N x M sliding window. N and M are odd numbers

SLIDING WINDOW Najeem Lawal, VHDL ET062G & ET063G Suggested implementation architecture 1.linebuffers 2.Boundary controller 3.Pixel switch 4.Filter function 5.Output synchronisation

SLIDING WINDOW Najeem Lawal, VHDL ET062G & ET063G –At the image edges –There are invalid pixel –How do you build a valid neighbouthood of pixels around edge pixels? –3 alternatives Avoid processing edge pixels Copy centre pixel to the invalid pixel locations Reflections. Default to 0 or 255

QUESTIONS Najeem Lawal, VHDL ET062G & ET063G Lecture 5 ABOUT FPGA / VHDL ABOUT VGA DISPLAY / TIMING ABOUT IMAGE SENSOR TIMING ABOUT RANGE SENSOR ABOUT LINE BUFFERS ABOUT MEMORIES & COUNTERS

END OF LECTURE 5 Najeem Lawal, VHDL ET062G & ET063G Lecture 5 OUTLINE –Test Bench –Clock generation –Reading BMP –Generating Control Signal –Testing the result