ECE 353 Introduction to Microprocessor Systems Discussion 11

Topics Interrupts and Exceptions Q&A

Interrupts and Exceptions The ADuC7026 defines locations for each exception vector – the code must put the proper instructions there to handle each exception. Table 2-4Table 2-4 ADuc7026.s places the address of the IRQ handler in the proper vector location. Exception.s contains the actual exception handler routines. The interrupt checklist posted on the course web page gives guidelines of what needs to be done to correctly handle interrupts. The ADuC7026 has 23 sources of interrupts. Table 72Table 72

Interrupt Problem Assume that the CPU is being clocked at 41.78MHz (32768Hz x 1275). Set up timer #1 to generate a periodic interrupt at a frequency of 3.2kHz. Produce an output on pin 4.0 that will have a duty cycle given by duty/32, where duty is a byte memory variable. The ISR can only make one change to the P4.0 state in each invocation. Only use the five least significant bits of duty.

Answer Requirements: Timer – setup to give a 3.2 kHz periodic interrupt Timer ISR – use to handle generating the proper output Variables – Count (for timer period tracking) and Duty (for setting the duty cycle) Output pin – P4.0

Answer In Main, we need: Setup GPIO for P4.0 Setup Timer1 Setup ISR Initialize variables In ISR, we need: Update count Update output

Answer Variables: Count – to get duty cycle increments of 1/32, we need to keep track of Timer ISR occurrences – Count will need values of Each execution of the Timer ISR will need to increment or decrement Count, and if it reaches the limit, reload the start count. Duty – Duty will be set in main – will determine how many of the 32 occurrences of the Timer ISR in one period will need to set the output high. (Timer ISR will not modify this variable.)

Answer Timer1 config: System clock at MHz means clock period of ns. Timer frequency of 3.2 kHz means timer period of us. Using divide by one, we need a T1LD value of us/ ns = ISR config: CLR Timer 1 IRQ Enable Timer 1 IRQ Enable global IRQ bit in CPSR (use MSR and MRS instructions) GPIO config: Set GPIO P4.0 as GPIO, output Initialize P4.0 to zero

Answer ISR details: Get Count and Duty variables Test: if Count < Duty, then P4.0 = 1, else P4.0 = 0 If Count == 0, then Count = 31, else Count = Count - 1 Store updated Count

ConcepTest What is the frequency of the output waveform? 3.2 kHz / 32 = 100 Hz What is the minimum average value? 0 What is the maximum average value? 31/32 = To achieve 1.0, we would need to relax the restriction on the bits of Duty to allow using 6- bits so we could go 0 – 32.

Answer Code: Main.s ; Filename: main11.s ; Author: ECE 353 Staff ; Description: main program file for discussion 11 ARM;use ARM instruction set EXPORT __main EXPORT Count EXPORT Duty INCLUDEaduc7026.inc ;count down, periodic, binary, source/1 T1CON_VALUEEQU0x000000C0 ;need interrupt every us with MHz clock T1_PERIODEQU13056 ;timer1 interrupt TMR1_IRQ_ENEQU0x AREA SRAM, DATA, READWRITE ; variables for timerISR DCountDCD0x0 ;timer ISR counter DDutyDCD0x0 ;duty cycle parameter

Answer Code: Main.s (cont.) AREA FLASH, CODE, READONLY __main ; setup GPIO pin 4.0 as output, initially zero LDRR7, =(GPIO_MMR_BASE);MMR base address MOVR0, #0x00 LDRR1, [R7, #GP4CON];get P4 as GPIO BICR1, R1, #3; STRR1, [R7, #GP4CON];set P4.0 as GPIO LDRR1, [R7, #GP4DAT] ;get P4 as GPIO ORRR1, R1, #0x ;set P4.0 as output BICR1, R1, #0x ;set P4.0 as zero STRR1, [R7, #GP4DAT] ; intitialize variables LDRR7, =(DCount);count address MOVR0, #31 STRR0, [R7];store initial count value LDRR7, =(DDuty);duty cycle variable address MOVR0, #20 STRR0, [R7];store initial duty cycle value

Answer Code: Main.s (cont.) ; setup timer1 LDRR7, =(TIMER_MMR_BASE);register base LDRR0, =(T1_PERIOD) STRR0, [R7, #T1LD];set timer period LDRR0, =(T1CON_VALUE) STRR0, [R7, #T1CON];configure timer ; setup interrupt LDRR7, =(IRQCON_MMR_BASE);register base MOVR0, #TMR1_IRQ_EN STRR0, [R7, #IRQCLR];clear timer1 interrupt STRR0, [R7, #IRQEN];enable timer1 interrupt MRSR1, CPSR; read CPSR BICR1, R1, #0x80;clear bit7 - IRQ disable bit MSRCPSR_c, R1; enable IRQs spin B spin CountDCDDCount DutyDCDDDuty END

Answer Code: Exception.s INCLUDE ADuC7026.inc;MMR definitions IMPORT Duty IMPORT Count IRQ_Handler PUSH{R0-R4};context save LDR R2, Duty LDRR0, [R2];get current duty cycle LDR R2, Count LDRR1, [R2];get current count LDRR3, =(GPIO_MMR_BASE) LDRR4, [R3, #GP4DAT] ;get P4 as GPIO CMPR1, R0; Count less than Duty - put out one BICPLR4, R4, #0x ;set P4.0 to zero ORRMIR4, R4, #0x ;set P4.0 to one STRR4, [R3, #GP4DAT] MOVSR1, R1;set flags MOVEQR1, #31;count at zero - reload SUBNER1, R1, #1;count not zero - decrement STRR1, [R2];store updated count ;interrupt stuff LDRR3, =(TIMER_MMR_BASE);timer MMR base address MOVR1, #0xFF STRBR1, [R3, #T1CLRI];reset timer1 interrupt POP{R0-R4};context restore SUBSPC, LR, #4 ;interrupt return

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