ECE2030 Introduction to Computer Engineering Lecture 16: Finite State Machines Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.

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ECE2030 Introduction to Computer Engineering Lecture 16: Finite State Machines Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2 Mealy and Moore Machines Combinational circuits Inputs X(t)Outputs Z(t) Storage Element S(t) MEALY MACHINE Z(t) =  {S(t), X(t)} Combinational circuits Inputs X(t) Outputs Z(t) Storage Element S(t) MOORE MACHINE Z(t) =  {S(t)}

3 State and State Diagram A state represents the machine snapshot at a given clock period A clock is typically used to synchronize the state transition A graph consists of a set of –Circles: Each represents a state Use double circle to represent the initial state –Directed arc: each represents a state transition –Inputs/outputs Mealy machine: –Label input/output along each arc Moore machine: –Label input along each arc –Label output inside the circle (i.e. state)

4 State Diagrams Example: State: S(t)  {S k, S j } Inputs: X(t)  {a, b} Outputs: Z(t)  {p, q} Initial state: S(0) = S k A Mealy machine exampleA Moore machine example SkSk SjSj a/p b/q b/p a/q a b S k /p S j /q b a

5 State Diagram Examples (Mealy) S0S0 S1S1 0/0 1/1 1/0 0/0 S0S0 S1S1 0/0, 1/1 0/0 1/0

6 State Diagram Examples (Moore) S 0 /1 S 1 / , S 0 /0S 1 /1

7 Design Example: Sequence Recognizer A sequential circuit that recognizes the occurrence of a particular bit sequence Input: X(t)  {0, 1} Output: Z(t)  {0, 1}

8 Sequence Recognizer Time X(t) Z(t)

9 Sequence Recognizer Time X(t) Z(t) S0S0 S1S1 1/0 0/0 S2S2 1/0 S3S3 0/0 1/0 0/0 1/1 A Meanly Machine

10 State Table 00 1/0 0/0 1/0 0/0 1/0 0/0 1/ Present State InputX Next State OutputZ P1P0N1N

11 Logic Circuits Design Steps Generate a Boolean function for –Each external output –Each state encoded bit Simplify the Boolean functions Draw a D F/F (or register) for each state encoded bit Draw logic circuits for –External outputs –Each inputs of state encoded bits –Input of state encoded bits = the next state –Output of state encoded bits = the current state

12 Logic Circuits Design Present State X Next State Z P1P0N1N X P1P0 N X P1P0 N0

13 Logic Circuits Design D0 F/F 11 22 P0N0 D1 F/F 11 22 P1N1 Z D0 F/F 11 22 P0N0 X

14 Example 2 Input: X(t)  {a, b, c} Output: Z(t)  {q, p}

15 State Diagram S EO /q A Moore Machine b S EE /p S OO /p S OE /p a a c b c a C b a b c

16 State Table 01/q b 00/p 10/p 11/p a a c b c a C b a b c Present StateInput (a, b, c)Next StateOutput P1P0X1X0N1N0Z S EE = 00 S EO = 01 S OO = 10 S OE = 11 a = 00 b = 01 c = 10 p = 0 q = 1

17 Logic Circuit Design Present StateInputNext StateOutput P1P0X1X0N1N0Z X X X X1 P1P0 X1X0 N X X X X0 P1P0 X1X0 N X X X X0 P1P0 X1X0 Z

18 Logic Circuit Design D1 F/F 11 22 P1N1 D0 F/F 11 22 P0N0 X1 X0 Z

19 Vending Machine State Machine Dispense a Coke when depositing 15 ¢ Inputs –5 = a nickel –10 = a dime –BC = bad coin (including quarters in this example) Outputs –R = reject –C = coke –N = no coke

20 State Diagram 0 ¢ BC/R 5 ¢ 5/N 10 ¢ 10/N 5/C 10/C 5/N BC/R 10/C BC/R

21 State Table 0 ¢ (00) BC/R 5/N 10/N 5/C 10/C 5/N BC/R 10/C BC/R Present State (0 ¢, 5 ¢, 10 ¢ ) Input (5 ¢, 10 ¢, BC) Next State (0 ¢, 5 ¢, 10 ¢ ) Output (C, N, R) P1P0X1X0N1N0C1C XX11XXXX 11XXXXXX 5 ¢ (01) 10 ¢ (10) 5: 00 10: 01 BC: 10 N: 00 C: 01 R: 10

22 Logic Circuits Design Present State InputNext StateOutput P1P0X1X0N1N0C1C XX11XXXX 11XXXXXX X X0 11 XXXX 10 00X1 P1P0 X1X0 N X X1 11 XXXX 10 01X0 P1P0 X1X0 N0

23 Logic Circuits Design Present State InputNext StateOutput P1P0X1X0N1N0C1C XX11XXXX 11XXXXXX X X1 11 XXXX 10 00X1 P1P0 X1X0 C X X0 11 XXXX 10 11X0 P1P0 X1X0 C0

24 Logic Circuits of the Vending Machine D1 F/F 11 22 P1N1 D0 F/F 11 22 P0N0 X1X0P0P1 C0 C1