Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres1 DC to DC Power Converion R. Ely and M. Garcia-Sciveres Atlas Upgrade Workshop Santa Cruz, November 2005 Series Scheme Charge Pumps Plans

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres2 Higher voltage power distribution is a MUST SCT SLHC (from Marc Weber’s Genova workshop talk) Read: voltage delivery at n times operating voltage

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres3 Two Options Serial Power Work started with Pixels. Demonstrated with present modules by Bonn group Picked up for SCT modules by Marc Weber at RAL Will be incorporated into stave prototypes DC-DC converters Proposed by LBNL Initial simulations shown at Genova (details later) No prototype yet due to lack of IC designer availability

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres4 First of all: Serial powering applies to modules, that is groups of chips on one hybrid connected to one sensor. Within hybrid, chips are powered in parallel !  one current source for a chain of modules; voltage defined by set of regulators  “ground levels” of any pair of modules vary

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres5 RAL work (Mark Weber) 4 SCT modules, serial powering PCBs, DAQ support cards SCT module 1 DAQ support card Serial powering PCB M4 M3 M2 DAQ support card Serial powering PCB

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres6 Schematics of serial powering PCB

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres7 Photograph of serial powering PCB Shunt regulator AC LVDS data Analog regulator AC LVDS Clock and command SCT module DAQ support card

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres8 Noise performance: indep. vs. serial powering Let’s look at noise occupancy (NO) first Module 662 powered independently Noise performance remains excellent ! Module 662 powered in series with 3 others

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres9 Noise performance: independent powering vs. serial powering Noise performance remains excellent Independently powered Powered in series

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres10 Noise performance: independent powering vs. serial powering Noise performance remains excellent Independently powered | Powered in series

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres11 Serial SCT plans from Genova  More studies on SCT module set-up (1-3 months) omore noise tests e.g. introducing noise sources/ oscillations ocloser look into AC-LVDS coupling  Built and study a more realistic system (½ -2 years) oDense packaging; oGrounding and shielding issues oMiniaturized regulator circuitry; oModified readout chip oRedundancy features  If promising, develop SLHC prototype (> 2 years)

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres12 DC-DC Converter options Switched Capacitor array –not common in industry except for divide by 2 –Seems natural choice for us- fewer worries (see below). Inductor Buck converter –typical in industry –We would have to worry about magnetic field, EMI from fringe fields, and would have to make our own air-core toroidal inductors.

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres13 Divide by 4 Stack Phase Load Vd Load Phase 2 4 capacitors – 13 switches

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres14 DC Converter - DC4x5 C2 1 C1 2 VSVS C0 C Z DC converter with 4 caps and an ideal conversion ratio of 5 10 switches Phase 1Phase 2 VSVS C3 C1 C2 C0C1 C3 C2 V V 2V 3V 5V C0

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres15 DC Converter – Div by 4 Ladder C4 Z C2 C C0 C3 C5 VSVS C3 C1 C4 C2 C0 VSVS C5 C3 C1 C4 C2 C0 Phase 1 Phase 2 6 Capacitors 8 Switches

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres16 Comparison of Circuits Normalize to Divide by 5 Stack5 caps 16 switches –Uniform charge on caps –Large voltage swings on switches DC4x5 4 caps 10 switches –2 caps have potential of 3Vo –Lower voltage swings on switches Ladder10 caps 12 switches –Larger potential differences on caps –Voltage swings on switches ~ Vo

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres17 CMOS Transistor Switches Austria Microsystems H35 Process –Feature size 0.35μ – 3 gate oxides – Vds up to 50 vts – Bulk isolation – Gate oxide breakdown vt > 8vts

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres18 AMS H35 Transistors Device Name Min. L (μ) Max. Vgs(vt ) Max Vds(vt ) On Res. L = min W= 50m C g (pf) NMOSI NMOS50 T PMOS50 T

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres19 Figures of Merit (for divide by n) Voltage efficiency - ε v = n*Vout / Vin – Vout is a function of the load = Vin / n for no load Current efficiency - ε I = Iout / n*Iin – Charge is lost charging the gate capacitance of the switches Power efficiency - ε p = ε v * ε I Ripple - less than Iout*period/C

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres20 Figures of Merit for Divide by n Stack Supplying Io (all switches have ‘on’ resistance R, all switched capacitors have value C and Co >>C) Low frequency limit – RC << 1/f Hi frequency limit - RC >> 1/f - clearly we want IoR << Vs/4 (for Vs = 10v, R < 2.5Ώ (For ladder)

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres21 Divide by 5 Stack

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres22 Drain-Gate-Source Waveforms of Switches

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres23 Efficiency versus Frequency

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres24 Efficiency vs Transistor Width

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres25 Power Efficiency

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres26 Buck Converter

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres27 DC Conversion Conclusions At an operating freqency of 5mhz (Co = 4.7uf, C1 = 0.2uf –Voltage efficiency ~.84 –Current efficiency ~.92 –Ripple = 1.2% –Output impedance = 0.25 ohms (25mv / 100ma) Clock generator will reduce efficiency by 10%

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres28 Other topics not related to power

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres29 Test of Indium Bumped “2E” Assembly Mask used for scans 2E = 2 columns per pixel. Only a small region of the sensor is properly bonded to the readout chip. The rest of the pixels are disconnected. The bonded region is shown here. X-axis is column number and Y- axis is row. Only the bonded channels were probed in what follows. Disconnected channels were masked off.

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres30 Noise vs. Voltage This is the most probable single channel noise for select connected pixels. Determined from s-curve fits in charge injection scans after tuning thresholds to 4000e. Looks like Depletion voltage at ~23 V Low voltage values not reliable due to bad S- curve fits

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres31 Representive S-curves at varying voltages Above depletioon voltage (~25 V) 12 V 3.5 V 0.5 V 6.5 V 2.0 V Corrected bias voltage

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres32 Short strip module geometry For a given hybrid technology, only way to reduce ratio (hybrid_mass)/(silicon mass) is to increase IC input density hybrid sensor IC Sensor is twice the strip length, With bond pads in the middle. stave Hybrid can neck down here to save mass

Nov. 10, 2005UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres33 Nanowire carpet hybrid pixel proposal Submitted to LBNL molecular foundry Too recent to know where this will go Eliminates bump bonding AND sensor wafer patterning. Intent is to produce very cheap hybrid pixel modules.