Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 16, 2012 Memory Periphery

Today Memory Periphery Driving Decode Sensing Energy (time permitting) Penn ESE370 Fall DeHon 2

Bus Drivers Penn ESE370 Fall DeHon 3

Memory Bank Penn ESE370 Fall DeHon 4

Tristate Driver Penn ESE370 Fall DeHon 5

Tri-State Drivers Penn ESE370 Fall DeHon 6

Memory Bank Penn ESE370 Fall DeHon 7

Row Select Logically a big AND –May include an enable for timing in synchronous Penn ESE370 Fall DeHon 8 How many transistors (per address bit)?

How tall is a row? Side length for cell of size: – – – Penn ESE370 Fall DeHon 9

10 How tall is an AND? Penn ESE370 Fall DeHon

Row Select How can we do better? –Area –Delay –Match to pitch of memory row Penn ESE370 Fall DeHon 11

Row Select Compute inversions outside array –Just AND appropriate line (bit or /bit) Penn ESE370 Fall DeHon 12

Row Select Share common terms Multi-level decode Penn ESE370 Fall DeHon 13

Row Select Same number of lines Half as many AND inputs Penn ESE370 Fall DeHon 14

Row Select: Precharge NAND Penn ESE370 Fall DeHon 15

Row Select: Precharge NOR Penn ESE370 Fall DeHon 16

Sensing Penn ESE370 Fall DeHon 17

Penn ESE370 Fall DeHon 18 SRAM Memory bit

Simulation W access =20 Penn ESE370 Fall DeHon 19

Sense Small Swings What do we have to worry about? Penn ESE370 Fall DeHon 20

Sense Small Swings Variation Common mode noise Penn ESE370 Fall DeHon 21

Differential Sense Amp Goal: –Reject common shift Penn ESE370 Fall DeHon 22

Differential Sense Amp Penn ESE370 Fall DeHon 23

What doe this do? Output when: –In=Gnd? –In=Vdd? –Transfer curve? Penn ESE370 Fall DeHon 24

“Inverter” Input high –Ratioed like grounded P Input low –Pulls itself up –Until V dd -V TP Penn ESE370 Fall DeHon 25

DC Transfer Function Penn ESE370 Fall DeHon 26

Differential Sense Amp Penn ESE370 Fall DeHon 27

Diffamp Transfer Function in=/in, looks like “inverter” Deliberately low gain in mid region Penn ESE370 Fall DeHon 28

Differential Sense Amp “Inverter” output controls PMOS for second inverter Sets PMOS operating point –current Penn ESE370 Fall DeHon 29

Differential Sense Amp What happens when o In=/in ? o /in > in? o /in < in? Penn ESE370 Fall DeHon 30

Differential Sense Amp View: –Current mirror –Biases where inverter operating Penn ESE370 Fall DeHon 31

Differential Sense Amp View: – adjusting the pullup load resistance –Changing the trip point for “inverter” Penn ESE370 Fall DeHon 32

DC Transfer /in with in=0.5V Penn ESE370 Fall DeHon 33

DC Transfer Various in Penn ESE370 Fall DeHon 34

DC Transfer Various in What is trip point when: In=0.3V? In=0.4V? In=0.5V? In=0.6V? In=0.7V? Penn ESE370 Fall DeHon 35

After Inverter Penn ESE370 Fall DeHon 36

Ramp 50mV Offset Penn ESE370 Fall DeHon 37

Closeup 50mV Offset Penn ESE370 Fall DeHon 38

Connect to Column Equalize lines during precharge Penn ESE370 Fall DeHon 39

Singled-Ended Read Penn ESE370 Fall DeHon 40

5T SRAM Penn ESE370 Fall DeHon 41

Single Ended Given same problems –How sense small swing on single-ended case? Penn ESE370 Fall DeHon 42

Single Ended Need reference to compare against Want to look just like bit line Equalize with bit line Penn ESE370 Fall DeHon 43

Split Bit Line Split bit-line in half Precharge/equalize both Word in only one half –Only it switches Amplify difference Penn ESE370 Fall DeHon 44

Open Bit Line Architecture For 1T DRAM Add dummy cells Charge dummy cells to V dd /2 “read” dummy in reference half Penn ESE370 Fall DeHon 45

Memory Bank Penn ESE370 Fall DeHon 46

Energy (Time Permitting) Penn ESE370 Fall DeHon 47

Single Port Memory What fraction is involved in a read/write? What are most cells doing on a cycle? Reads are slow –Cycles long  lots of time to leak Penn ESE370 Fall DeHon 48

ITRS nm Penn ESE370 Fall DeHon 49 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV C 0 =  m × C g,total

High Power Process V=1V d=1000  =0.5 W access =W buf =2 Full swing for simplicity C sc = 0 –(just for simplicity, typically <C load ) BL: C load =1000C 0 ≈ 45 fF = 45× F W N = 2  I leak = 9×10 -9 A P= (45× ) freq ×9×10 -9 W Penn ESE370 Fall DeHon 50

Relative Power P= (45× ) freq ×9×10 -9 W P= (4.5× ) freq + 9×10 -6 W Crossover freq<200MHz How partial swing on bit line change?  Reduce dynamic energy  Increase percentage in leakage energy  Reduce crossover frequency Penn ESE370 Fall DeHon 51

Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process or transistors with high V th –Reduce leakage at expense of speed Penn ESE370 Fall DeHon 52

Idea Minimize area of repeated cell Compensate with periphery –Amplification (restoration) Match periphery pitch to cell row/column –Decode –Sensing –Writer Drivers Penn ESE370 Fall DeHon 53

Admin Monday: in Detkin Lab –Read lab2 assignment before coming to class Tuesday: Proj2 Milestone due Wednesday: Lecture Thursday/Friday: Thanksgiving Holiday Penn ESE370 Fall DeHon 54